Monolithic vs non-Monolithic FPGA

Hello,

From what I understand (and please correct me if I'm wrong),
1. Altera uses a single Monolithic piece of silicone for the manufacturing of its FPGA.
2. A Xilinx device (from series 7 and beyond) is actually an "FPGA array" - many similar pieces of silicon interconnected between them.

Intuitively, I think the first approach will allow easier routing (again, might be wrong here).
What do you think? Is it the case?
From the logic designers point of view - what are the disadvantages of working with a non-monolithic device ?

Depending on how they are connected, i.e., some form of 3d stack or interposer, there will be very little concern to the designer.

the tool will allocate logic accordingly and try to keep critical timing paths within the same region. routing resources are different intra chip and inter chip, but again, the tool will make those decisions for you.

A Xilinx device (from series 7 and beyond) is actually an "FPGA array" - many similar pieces of silicon interconnected between them.

Click to expand...

Hardly. Would make no sense at all.

If you see any indication for this speculation, please post a link.

this might be of help: https://www.altera.com/content/dam/...nabling-nextgen-with-3d-system-in-package.pdf

I see, they put multiple chips in a package for the largest devices, called "3D" chips. As ThisIsNotSam shows, it's the next generation technology also at Altera.

At Xilinx, only a small part of 7 series is made in this way.

For Xilinx this is referred to as SSI (Stacked Silicon Interconnect) and is restricted to the largest devices they make. These parts typically have restrictions on clocking and number of signals that cross the SSI bridging between die. I'm sure Altera parts suffer from the same kinds of issues. The primary driver for Xilinx switching earlier than Altera was because they didn't want to have yield issues with such a large die (like the ones Altera was producing for their largest parts). Most of this was based on discussions with the regional FAE that I used to have lunch with on a semi regular basis a number of years back (I doubt much has changed over the past 3-4 years).

Most of the parts Xilinx produces are monolithic though they may not look like it as they use a cookie-cutter approach to the design of clock regions. It is the primary reason once they introduce the first in a new series of parts they can fill out the entire family in a few months (usually). The design of larger a part just requires more of the tiles they created for the die. Back when they started this in the Virtex 4 timeframe Altera was still creating all their parts with their I/O on the periphery of the die and each part had a completely different die with pretty much no commonality with another part in the same family.

Hardly. Would make no sense at all.
If you see any indication for this speculation, please post a link.

Click to expand...

It's mentioned in this interesting video - unfortunately it's rather long I don't remember when...
https://www.youtube.com/watch?v=U_16tKynK7Y

The larger Xilinx devices will use an interposer. Smaller devices will not. IIRC, Xilinx has limits on long links between these layers. Overall, the interposer is a wonderful idea. Eventually we will get local DRAM and possibly other ASICs.