modulo operator doubt

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vinodkumar

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xst:1763

HI friends IS modulus operator,x modulo y is synthsizable,i find it not where x and y are integers,then how to get synthesizable HW for modulo operator.


byeee
 

hi


yes synthesizable.:idea:
 

for integer and std_logic_vector work, for real not ok
 

Hi i wrote the code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_unsigned.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity modulo is
port(a,b:in integer;
cut integer
);
end modulo;

architecture Behavioral of modulo is

begin

c<= a mod b;


end Behavioral;

the error i got is:


ERROR:Xst:1763 - "D:/modulo/modulo/mod.vhd" line 42: Operator <MODULUS> must have constant modulo operand.
-->
 

Hi,
Your error means that you cannot have 'b' as variable, and b cannot be anything other than a power of 2. If you do

c<= a mod 2 or
c<= a mode 2^n.
Kr,
Avi
http://www.vlsiip.com
 

hi actually i want to do a mod 100,a mod 1000 like tht.byee
 

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