HI friends IS modulus operator,x modulo y is synthsizable,i find it not where x and y are integers,then how to get synthesizable HW for modulo operator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_unsigned.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity modulo is
port(a,b:in integer;
cut integer
);
end modulo;
architecture Behavioral of modulo is
begin
c<= a mod b;
end Behavioral;
the error i got is:
ERROR:Xst:1763 - "D:/modulo/modulo/mod.vhd" line 42: Operator <MODULUS> must have constant modulo operand.
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