Module replication in verilog

I wanted to create multiple instances(lets say 100, 1000 and increasing on) of the 8 bit LFSR. I have used the generate statements but I am getting errors. If someone could help with the generate statement syntax:


module top(clock,outpath);
parameter N=100;
input clock;
output [8*N-1:0] outpath;
genvar i;
generate
for (i=0; i<N; i=i+1) begin : lfsr_flops
LFSR8_8E u (clock,outpath[8*i+7:8*i]);
end
endgenerate
endmodule




module LFSR8_8E(clock,q);
input clock;
output [7:0] q;

reg [7:0] LFSR;
wire feedback = LFSR[7];

always @(posedge clock)
begin
LFSR[0] <= feedback;
LFSR[1] <= LFSR[0];
LFSR[2] <= LFSR[1] ^ feedback;
LFSR[3] <= LFSR[2] ^ feedback;
LFSR[4] <= LFSR[3] ^ feedback;
LFSR[5] <= LFSR[4];
LFSR[6] <= LFSR[5];
LFSR[7] <= LFSR[6];
end

As we are not in a guessing game, you may want to mention an actual error message. I see that in the LFSR module, q is unconnected, so the synthesized design will reduce to nothing.

Furthermore I don't understand the design purpose because all LSFR instances will have exactly the same output with q connected.