Modified Full Bridge SMPS for high power without the headaches?

[treez]

Hello,
Do you believe that this “Modified Full Bridge” SMPS (as in attached pdf schem and LTspice sim) is a good idea for when power is >500W?
This Full Bridge has an extra added external “leakage inductor”, -the reason for this is so that…

1…The secondary diodes have a much softer recovery (it’s as soft as if a PhaseShiftFullBridge were being used.
2….This “leakage” inductor means that there are virtually no overlap switching losses in the primary side FETs (only capacitive switching losses from the discharge of Cds)

The “leakage inductor” doesn’t have to be as high_Henry_value as it would be if a PhaseShiftFullBridge were being used…so therefore there are less secondary side diode snubber issues to worry about.
Also, the diodes to the rails seen in the primary side are to act as a freewheel path for the “leakage inductor” current, so as to stop it being passed through the transformer and ending up being snubbed out into the diode RC snubbers.

One of the key issues, is that this “Modified Full Bridge” SMPS, is a good competitor to the PhaseShiftFullBridge, because the PhaseShiftFullBridge suffers from potential latchup of the primary side FETs due to the reverse recovery of the intrinsic diode in the FET. –This “Modified Full Bridge” SMPS does not suffer from this issue. This is because there is not an interval of FET conduction immediately following the interval of conduction by the FET’s intrinsic diode….and as you know, in the PhaseShiftFullBridge, the latchup of the parasitic BJT internal to the primary FET, which happens when the FET is conducting immediately after the reverse recovery of the intrinsic diode is the big weakness of PhaseShiftFullBridge converters.

Yet another advantage of the “Modified Full Bridge” SMPS over the PhaseShiftFullBridge is that there is less circulating primary current, and also the “Modified Full Bridge” can use FETs with a much lower Rds(on) and doesn’t have to need a FET with a super fast intrinsic diode (as does a PhaseShiftFullBridge) .
-If you run the simulation, you willl actually see how the reverse recovery of the intrinsic diode of the primary FETs is very soft, and is just done by the “ring up” of the LC between the “leakage inductor” and the FET Cds’s.

So do you believe that this “Modified Full Bridge” SMPS is a genuine competitor to the PhaseShiftFullBridge?

 

[Easy peasy]

If the o/p diodes carry any reverse current at all, this will be seen in your leakage inductor, it will cause big spikes on the diodes when they finally snap off...(i.e. you'll need much bigger snubbers on the diodes, for volt safety and RFI) When the mosfets turn off there will be significant "drive" from this inductor causing the mosfets not to turn off into half rail (perfect hard switcher) but nearer full rail, upping turn of losses, hence bigger snubbers needed on the mosfets too (for RFI).

Also the mosfet drain-source voltage can now collapse very fast at turn on for agressive gate drive, => more RFI..!, unless the bigger snubbers are there on the fets...

Build it and you will see, it is exactly the same as having a fair bit of leakage in the Tx, except not so well coupled to the sec...

 

[treez]

When the mosfets turn off there will be significant "drive" from this inductor causing the mosfets not to turn off into half rail (perfect hard switcher) but nearer full rail, upping turn of losses, hence bigger snubbers needed on the mosfets too (for RFI).

Whereas I can well see the point you are making here, if this were really an issue then all Full Bridge transformers would get interleave wound for low-as-possible leakage inductance.
….Not only that, but if you consider the fet turn-off in a Phase Shift Full Bridge converter, then that has exactly the same problem that you describe…and nobody seems too bothered about it there.

Also the mosfet drain-source voltage can now collapse very fast at turn on for agressive gate drive, => more RFI..!, unless the bigger snubbers are there on the fets...

Thanks, but in a “Normal” Full Bridge (without the external “leakage inductor”), the Vds can still collapse at a high rate for such aggressive gate drive. However, since the leakage inductance slows up the rise of FET current at switch on, there won’t be any need for fast gate drive for turn-on.

Build it and you will see, it is exactly the same as having a fair bit of leakage in the Tx, except not so well coupled to the sec...

…Not having the external “leakage inductor” so well coupled to the secondary sounds a good thing, since it will mean less ringing on the secondary diodes

- - - Updated - - -

If the o/p diodes carry any reverse current at all, this will be seen in your leakage inductor, it will cause big spikes on the diodes when they finally snap off...(i.e. you'll need much bigger snubbers on the diodes, for volt safety and RFI)

Thanks, great point, I had inadvertently used the wrong type of diodes in the simulation, and forgot to include that there would be the intrinsic (unfortunately high trr) diodes in the synchronous FETs. So yes, there will indeed be this greater ringing across the secondary diodes, and as such, I have included the regenerative snubber into the schematic of the “Modified Full Bridge SMPS”. (updated LTspice simulation and pdf schematic of “Modified Full Bridge” SMPS attached.).

The point is though, that the Phase Shift Full Bridge also has exactly the same problem of high secondary diode snubber dissipation. –Therefore, in this respect, the Phase Shift Full Bridge SMPS has not “trumped” the “Modified Full Bridge” SMPS. The reason for the “Modified Full Bridge” SMPS is to get high power without the problems of FET failure which are inherent to the Phase Shift Full Bridge SMPS

 

[FvM]

FET failure which are inherent to the Phase Shift Full Bridge SMPS

Misleading words. There's a risk of failure only when exceeding the intrinsic diode recovery dV/dt maximum rating. Need to design your gate driver circuit respectively.

 

[treez]

Yes indeed I see your point, and you are indeed correct.. ..the dv/dt of the FET Vds at turn_off (in the Phase Shift Full Bridge) can indeed be reduced by ‘damping’ the gate drive to slow down the drain voltage transition. –This reduces the problem of FET failure in the Phase Shift Full Bridge. However, as you know, that means more switch-off switching loss. –The thing is, you don’t need to do that in the “Modified Full Bridge” SMPS because the FETs are under conditions which mean they are more likely to have adequately reverse recovered by the time turn_off happens. So you can turn-off the FETs of the “Modified Full Bridge” SMPS quicker and not worry about FET failure.
..And as a consequence the “Modified Full Bridge” SMPS means you get less turn-off switching losses than with the Phase Shift Full Bridge SMPS.

 

[FvM]

Violation of reverse recovery dV/dt can only happen during hard turn-on of the opposite FET, thus it has to be avoided by slowing down turn-on. Involves some additional losses of course.

 

[treez]

yes i agree, and of course, slowing down turn-on in the "Modified Full Bridge" SMPS is no problem, because the leakage inductance means there's no current in the fet at the instant of turn_on.