wtr
Full Member level 5
The following is the dump
vsim -L work test.sd_cmd_master_tb
# vsim -L work test.sd_cmd_master_tb
# Start time: 16:38:27 on Jan 03,2018
# Loading sv_std.std
# Loading test.sd_cmd_master_tb
# ** Error: (vsim-3033) ../../../bench/verilog/sd_cmd_master_tb.sv(72): Instantiation of 'sd_cmd_master' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /sd_cmd_master_tb File: ../../../bench/verilog/sd_cmd_master_tb.sv
# Searched libraries:
# C:/fpgamason/memory/sd_card_controller/trunk/sim/rtl_sim/run/test
# C:/fpgamason/memory/sd_card_controller/trunk/sim/rtl_sim/run/test
Notice that it doesn't look in the work library but rather the test library twice.
to put into context the following works
vmap diff_name work
vsim -L diff_name test.sd_cmd_master_tb
# vsim -L diff_name -L test test.sd_cmd_master_tb
# Start time: 16:46:34 on Jan 03,2018
# Loading sv_std.std
# Loading test.sd_cmd_master_tb
# Loading diff_name.sd_cmd_master
vsim -L work test.sd_cmd_master_tb
# vsim -L work test.sd_cmd_master_tb
# Start time: 16:38:27 on Jan 03,2018
# Loading sv_std.std
# Loading test.sd_cmd_master_tb
# ** Error: (vsim-3033) ../../../bench/verilog/sd_cmd_master_tb.sv(72): Instantiation of 'sd_cmd_master' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /sd_cmd_master_tb File: ../../../bench/verilog/sd_cmd_master_tb.sv
# Searched libraries:
# C:/fpgamason/memory/sd_card_controller/trunk/sim/rtl_sim/run/test
# C:/fpgamason/memory/sd_card_controller/trunk/sim/rtl_sim/run/test
Notice that it doesn't look in the work library but rather the test library twice.
to put into context the following works
vmap diff_name work
vsim -L diff_name test.sd_cmd_master_tb
# vsim -L diff_name -L test test.sd_cmd_master_tb
# Start time: 16:46:34 on Jan 03,2018
# Loading sv_std.std
# Loading test.sd_cmd_master_tb
# Loading diff_name.sd_cmd_master