Modelsim vs. Xilinx ISim

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spman

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Hi

Which one is better?
Isim is more convenient and easy for me. I don't know why it is said that Modelsim is more professional. What does Modelsim have more than Isim? Perhaps I don't know Modelsim capabilities!

And another question! What is difference between Modelsim SE, PE and DE? I didn't find any useful information at model.com!

Thanks in advance
 

Modelsim is more powerful. It has full VHDL 2008 support, code coverage, mixed language capability (THough Im sure ISIM has too), it will actually let you read data files in VHDL, code profiling and plenty of stuff Ive never used.

The main differences between PE (sometimes labelled the Pauper's Edition), SE and DE is speed - the more the pay, the quicker your simulations, and SE and DE have features that PE does not.

But if all you want to do is similate basic testbenches, ISIM is fine.
 
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    spman

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Isim indeed has the convenience going for it, and it's fine for basic testbenches. Modelsim however supports System Verilog, isim doesn't.
 
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    spman

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I also get the feeling Isim wont support all of VHDL (like protected types) as I got a few bugs in modelsim fixed, and modelsim is usually the best for supporting all language features. But then no one uses protected types except me....
 
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Modelsim SE is no longer offered. The key advantages of DE over PE is performance, Linux platform support, and SystemVerilog assertion support.

All versions of Modelsim support all of SystemVerilog except constrained random generation, functional coverage and assertions.

Things that you do not get with most free versions of simulators are: code-coverage analysis, regression test tracking(which tests can I run to get the most coverage fastest), PLI/VPI/DPI integration
 
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    spman

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Thanks for your responses

I have a design containing DDR3 RAM. Simulation of the design takes a long time in behavioral mode. About 10 min! So I installed Modelsim SE 10 and I'm trying to simulate the design with it. But some errors appear during compilation. For examples Modelsim doesn't accept redeclaration of an output as register (or wire) in verilog! why?!
 

Simulation of the design takes a long time in behavioral mode. About 10 min!
Click to expand...

10 minutes. Thats positively short!.

Why not post the code and the error?
 

The code is too long. It's something like this :

Code: 
module myModule(Clk, PortA, PortB);
input Clk;
input PortA;
output PortB;

reg PortB; // The error is appeared here

always @...
...
Error:
'PortB' already declared in this scope (example_top).
Click to expand...

Also there is another type of error when I use words that I have decleared by `define !
A part of code :
Code: 
...
		else if (State == 2)
		begin
			if (app_wdf_rdy)
			begin
				//app_wdf_data <= ~(256'b0);
				DataIndex	<= DataIndex + 1;
				app_wdf_end	<= 1;
				app_addr	<= app_addr + 8;
				app_cmd		<= `cmd_Write;  //Error is appeared here
				app_en		<= 1;
				State		<= 3;
			end
		end
...
Error :
A begin/end block was found with an empty body. This is permitted in SystemVerilog, but not permitted in Verilog. Please look for any stray semicolons.
Click to expand...

This design was being simulated by Isim without any error!
 

So declare PortB as a reg in 1 declaration. Like so:

Code: 
output reg PortB;

As for defines ... as a general practice you are better of using parameters for things like that.

Code: 
parameter CMD_WRITE = 16'hCAFE; // somewhere at the start

...

app_cmd		<= CMD_WRITE;  // Error may still appear here, who knows. :P But at least one crappy define less in the universe.

And if the scope of this parameter is local, you might want to use a "localparam" instead of "parameter".
 
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Much better to use the Verilog-2001 version of port declarations (supported for 12 years now :!: ). Then you only need to declare an identifier once.

Code: 
module myModule(
  input Clk, // 1 bit wire is the default
  input wire PortA,
  output reg PortB
);
 
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    spman

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@spman,

Have you considered Active-HDL from Aldec. https://www.aldec.com/en/products/fpga_simulation/active-hdl

It offers many benefits over ISim. It actually matches quite well with Modelsim but also has many unique features - e.g you can import legacy schematic Xilinx designs into it if you wan to re-target the device. Active-HDL also has different configuration that matches with FPGA vendor tools. Just take a look at https://www.aldec.com/en so you can make an informed decision.
 

Modelsim simulated my design in one minute! The design had been simulated in 10 minutes by Isim for behavioral mode! Also with Modelsim I could do post route simulation that was not possible by Isim because of too slow simulation speed.

Now I have a problem in post route simulation. The design works correctly during behavioral simulation and also on FPGA after configuration. But doesn't work correctly in post route simulation! I found out that the ddr_reset_n signal is not asserted in post route simulation. The signal is output of a ODDR primitive. What's the problem?

Code: 
  ODDR #
    (
     .DDR_CLK_EDGE ("SAME_EDGE"),
     .INIT         (1'b0),
     .SRTYPE       ("ASYNC")
     )
    u_out_reset_n
      (
       .Q  (ddr_reset_n),
       .C  (clk),
       .CE (1'b1),
       .D1 (mux_reset_n),
       .D2 (mux_reset_n),
       .R  (rst_r),
       .S  (1'b0)
       );
 


I also am an Active-HDL user. When we were first looking at simulators, Active-HDL was a lot less expensive than Modelsim, and I find it a lot easier to use. I mean A LOT. Modelsim may have features that Active-HDL doesn't, but I haven't missed them. Also, you can use Active-HDL as your development environment-do all your editing (with syntax checking, formatting, etc.), simulation, implementation from a single environment; I'm not sure if ModelSim provides that capability.
 
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    spman

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Could anybody help me about my last post?
What is the ODDR primitive? Why doesn't work in post route simulation?

Thanks
 

Too lazy to type. Plenty of readily available information from xilinx. https://www.google.com/search?q=xilinx+oddr+primitive

ODDR's work fine in post route sim as far as I know. Did you run the not-working sim in ISE or Modelsim? Also, what version?

That, and please post a somewhat complete testbench code + screenshot of the offending bit of simulation. Saves a lot of guessing.
 

In ISE, or in Vivado? ISE 14.1 doesn't support SV as far as I know. Or maybe you mean isim 14.1 for SV simulation?
 

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