ModelSim, unexpected output value

[echo47]

I'm running ModelSim SE 5.8d on Win2k. Why does this Verilog 2001 module return the value 49 instead of 35?

module foo (y);
  wire   signed [15:0] a, b;
  output signed [15:0] y;

  assign a = 5;
  assign b = 7;
  assign y = 1 * a * b;
endmodule

 

[z81203]

ModelSim, unexpected output value.

interesting, the problem is 1 or signed.
for signed, if you try 1*b*a, it's 25; & if you write 16'd1, there is no problem.
for unsigned, there is right also.
i don't know why. who can explain it?

 

[nand_gates]

This is possibly a bug in Modelsim version you are working with.
I am getting correct result on ModelSim SE vlog 5.5d Linux

 

[z81203]

hi, i try it with 6.0b on sun. same problem.

 

[nand_gates]

Ya,

Ur right on Modelsim 6.0b linux its giving wrong response!