[SOLVED] Modelsim Simulate Vivado DDR4 Env Failed

luoyanghero · Nov 25, 2016

env:vivado201603, modelsim 10.4 se win64

I have used modelsim compiled vivado library, and simulated a core generated fifo
using modelsim, it is OK.

Now I core_gen a ddr4 with axi interface, I use modelsim to simulate, failed.

1.modelsim command script as follow:

Code Verilog - [expand]
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vlog -sv -timescale 1ns/1ps -f flist.f
// flist.f...
./tb_top.v
../x/sim_ddr.srcs/sources_1/ip/ddr4_0/rtl/ip_top/ddr4_0.sv
// end flist.f...
vsim -gui -novopt work.tb_top

2.The error as follows:

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Error: (vsim-3033) ../x/sim_ddr.srcs/sources_1/ip/ddr4_0/rtl/ip_top/ddr4_0.sv(151): Instantiation of 'ddr4_0_ddr4' failed. The design unit was not found.
#    Time: 0 ns  Iteration: 0  Instance: /tb_top/u_ddr_wrap/u_ddr4_0 File: ../x/sim_ddr.srcs/sources_1/ip/ddr4_0/rtl/ip_top/ddr4_0.sv

3.I know in modelsim need add a option to include xilinx lib, for example a

fifo: '-L fifo_generator_v13_1_2 '.

But I don't know the specified lib for
ddr4. I tried to include all xilinx lib, it not success.

4.Follow the errors, I try to add module ddr4_0_ddr4 in the relative files:

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ddr4_0/rtl/ip_top/ddr4_0_ddr4.sv
ddr4_0/rtl/ip_top/ddr4_0_ddr4_mem_intfc.sv
ddr4_0/rtl/ip_top/ddr4_v2_1_0_ddr4_assert.vh

There are more errors than before.

5.I try to use vivado simulating ddr4, it can work.

How should I do in modelsim environment to simulate ddr4?

[SOLVED] Modelsim Simulate Vivado DDR4 Env Failed

luoyanghero

Junior Member level 3

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Code Verilog - [expand]
1 2 3 4 5 6	vlog -sv -timescale 1ns/1ps -f flist.f // flist.f... ./tb_top.v ../x/sim_ddr.srcs/sources_1/ip/ddr4_0/rtl/ip_top/ddr4_0.sv // end flist.f... vsim -gui -novopt work.tb_top

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1 2 3	ddr4_0/rtl/ip_top/ddr4_0_ddr4.sv ddr4_0/rtl/ip_top/ddr4_0_ddr4_mem_intfc.sv ddr4_0/rtl/ip_top/ddr4_v2_1_0_ddr4_assert.vh

[SOLVED] Modelsim Simulate Vivado DDR4 Env Failed

luoyanghero

Junior Member level 3

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