Modelsim or Silos Which one is better for Verilog Programming

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moonnightingale

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Modelsim or Silos Which one is better for Verilog Programming.
I also want to run testbenches
 

Hi

modelsim is the defacto of HDL world. Good and easy usage, fine waveform viewer and popularity.
it also in main stream of tools for mentor graphics. for example mentor Questasim is for verification.


tnx
 

hi
modelsim is very good design software. you use the modelsim as simulation purpose. it give the waveform of your project.it use for verilog or vhdl both.
 

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