[SOLVED] ModelSim is not reporting errors properly

[tahirsengine]

Hi,
I am using ModelSim 18.1 for the simulation of my designs. Now the problem is I have some fairly obvious mistakes, and upon compile, ModelSim is skipping them and is not reporting the errors.

For example, I have a Verilog module like this:

module a_module(a,b,c,d);

I am instantiating this module like that:

a_module a_module_inst( .e(...),  .b(...),  .c(...),  .d(...));

In the port list above, e I/O is obviously not the part of original module. But ModelSim is compiling it properly.

Is there any option that I should choose to make ModelSim report errors?

 

[wwfeldman]

did a different error show up a few lines later?
sometimes the error found is not the syntax error you're talking about, but an error as a result of the syntax error.

 

[tahirsengine]

did a different error show up a few lines later?

No, nothing appeared. Basically it is compiling without any error. I don't know why its not detecting errors. It is detecting some other errors, though.

 

[FvM]

Modules are compiled separately, the error will pop up when you simulate (.e.g module "not bound" error). That's how the simulator works. There will be surely an error message, just read the simulation log thoroughly.

 

[tahirsengine]

Modules are compiled separately, the error will pop up when you simulate (.e.g module "not bound" error). That's how the simulator works. There will be surely an error message, just read the simulation log thoroughly.

You are right. When codes simulated, it gave an error. Thanks.