[SOLVED] modelsim: Illegal output or inout port connection

[ramanandn]

Hi guys,

I have an output port (reg) in a module. That module is instantiated in my top level module, with that output signal as wire to a pin on the CPLD.

I don't assign anything to this in my tb (since it would be an input into the tb).

But I still get the above error from Modelsim. The compilation goes through fine which makes me think that my tb has an issue. But I do nothing with this signal in my tb.

Any thoughts?

 

[FvM]

The top level pin must be either in- or output. If it's input, you get an error.

 

[ramanandn]

Sorry I didn't understand. The top level pin cannot be input??!

 

[FvM]

Right, a pin wired to an output of a lower level entity or a register at the top level entity can't be of the input type.

 

[ramanandn]

I understand that.. it is still output out of the top level. It is input to the testbench. I don't use it in the tb.

 

[ramanandn]

Anyone please?

 

[FvM]

According to your description, there should be no error.

 

[alexan_e]

I have an output port (reg) in a module.
I don't assign anything to this in my tb (since it would be an input into the tb).

you are using a reg instead of a wire in your testbench, that's the only way to get this error.

Alex

 

[yadog]

i didnot quite follow what you said,maybe you can shou some code of your design.

just note that:in testbench,there should be only reg or wire,that is,if a signal in your design project is declared as input,then in your testbench,you should define it as reg;otherwise,define it wire.No tri-state in testbench!

hope it helps