jamesyang1209
Full Member level 1
modelsim waveform dump
Dear Group,
I have two questions (has some relation):
1. I know how to dump fsdb file for bench written in verilog, but how about bench (and RTL) written in VHDL?
2. In order to solve above question, I add a verilog bench (inserted module is written in VHDL). After dumping, open fsdb by debussy only can see the signals for verilog bench (can't see any signals for VHDL module). Why?
In verilog bench, I use
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(test);
end
And, I add "-pli novas.dll" in modelsim options.
Any step I do wrong?
Thanks.
James.
Dear Group,
I have two questions (has some relation):
1. I know how to dump fsdb file for bench written in verilog, but how about bench (and RTL) written in VHDL?
2. In order to solve above question, I add a verilog bench (inserted module is written in VHDL). After dumping, open fsdb by debussy only can see the signals for verilog bench (can't see any signals for VHDL module). Why?
In verilog bench, I use
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(test);
end
And, I add "-pli novas.dll" in modelsim options.
Any step I do wrong?
Thanks.
James.