If it is a PDSOI process then pick a JI of similar voltage
range, dummy out the well-substrate params and replace
with a plain capacitance of sensible area and t=~1um.
Because these deeper body flows look like regular MOS
pretty much, only the well is freed up.
FDSOI, it gets messy. BSIM won't cut it, BSIMSOI is a
bit buggy, and anybody in this space is sensitive to
competition so unlikely to share anything with a non-
customer (vetted, too).
But if you were good at model fitting, again you could
take a roughly right geometry / voltage-node model
from some other foundry, shrink the S, D - body diodes
to one edge of sidewall, throw away the well-substrate
stuff and tweak until you see advertised fmax and any
other DC curves you can lay your hands on. Of course
you'll get no help at all on the back interface which is
the "secret sauce" and/or trouble a lot of the time.
I'd say if the problem is that you're not for real, so no
foundry will provide you models, then faking it will be
good enough.