Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

modeling clock in cadence

Status
Not open for further replies.
C

ccw27

Full Member level 5
Full Member level 5
Joined
Oct 13, 2004
Messages
267
Helped
14
Reputation
28
Reaction score
6
Trophy points
1,298
Activity points
2,558
How can I model a non-ideal clock in Cadnece? With skewness, jitter, etc ...

Thanks
 

Try looking into vpwm sorce. You can model jitter and other stuff in that
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top