model\sim Vs Active\H\DL

[eda_wiz]

aldec modelsim

hi,
Which is a better choice and why?

I have used both I feel activehdl is more easy to use .
Anyway I would like to know your comments

tnx

 

[Phytex]

modelsim + stil

Hi,

in my job, I use ModelSim. I don't know very much about Active HDL, but I think if you know something about VHDL or Verilog Modelsim is very easy to use. You have to read how to create testbenches under VHDL or Verilog, then Modelsim is really easy to use!!

Phytex

 

[linuxluo]

modelsim vs activehdl

Hi,
Modelsim is difficult for newbie, and activehdl is easy to master. but as to simulation performace and function, modelsim is stronger than activehdl. And most of all, modelsim is signoff tool, but active is not.

 

[snakebites]

modelsim,waveform editor ,key

ActiveHDL is easy for newbie, but I think Modelsim has some special functions.

 

[my_garden]

I use m/o/d/e/l/s/i/m. It is very good.
It has many good functions.
But it is difficult to learn it.

 

[dd2001]

ActiveDHL good for Newbie

Newbie can spend less time to use ActiveHDL, ver5.1 also easy to use. most small project can be done by ActiveHDL in a very short time. However, ModelSim need a long learn curve, the bad thing is you have to build stimulate table by text editor, that is particularly diffcult for newbie. ActiveHDL create stimulate by timing diagram.

 

[Amuro]

You can combine ActiveHDL and ModelSim seamlessly. Just create everything with ActiveHDL and then simulate with ModelSim. It would be better, isn't it?

 

[z81203]

i heard riviera has waveform editor, sometimes it's useful.

 

[sisari]

Modelsim vs. Active HDL

I think with Modelsim you can do pre and post synthesis simulations (even post-layout) because it allows SDF backannotation.
Active HDL doesn't have this but is better for code-writing than Modelsim
(templates, a more easy to use interface).

 

[buzkiller]

Active is almost as fast as Modelsim and is much easier to use. It also has many features that Modelsim doesn't. It's equal to Modelsim+HDL Designer.

 

[zoovy]

Re: Modelsim vs. Active HDL

I think with Modelsim you can do pre and post synthesis simulations (even post-layout) because it allows SDF backannotation.
Active HDL doesn't have this but is better for code-writing than Modelsim
(templates, a more easy to use interface).

I use ActiveHDL and SDF simulation is possible in ActiveHDL.

 

[eda_wiz]

Hi,
Yes SDF simulation is possible in @ctvieHDL and it is faster in simulation speed than Modelsim and has very good features .


But I dont know WHY modelsim is the popular choice for companies. Is it due to the past reputation.

TNX

NB: a simulation with modelsim gui is difficult . When you force a signal high or low all the windows automatically get minimised. consider a case when we are manually giving the inputs.

first we have to apply the reset then relase then asset other pins....
this is difficult with modelsim gui for sure

But in @ctive HDL you have a HOTKEY feature whic allows you to change the signal values from the key board during the simulatio is going on.

I am not using scripts to assert deasset the signals.



EVEN with all this features... STIL M0del\SIM is the popular one whyyyyyyyyyyy

 

[zoovy]

Hi,
Yes SDF simulation is possible in @ctvieHDL and it is faster in simulation speed than Modelsim and has very good features .



EVEN with all this features... STIL M0del\SIM is the popular one whyyyyyyyyyyy

I think there are numerous reasons
1) Modelsim was the first in the market.
2) People familiar with Asic world used to use Modelsim.
3) Recent divorce of Xilinx<->Aldec caused more grief. Modelsim can be executed inside the Xilinx tools. Aldec's approach was to build a shell to run xilinx tools inside Aldec environment. But it costed them to play catchup. When a version of Xilinx tools comes up Aldec is 3 months behind in supporting it.
4) Modelsim is more expensive. Therefore people think they get more when they pay more.
5) The misinformation and/or no-information but guesswork is in play as sisari wrote. (I don't mean to offend you sisari). Sometimes this is also half-true too. Maybe some point in time Aldec really did not support this feature or this feature was very difficult/awkward to use.

When making decision, I usually do an analysis at the time (checkpoint analysis). I don't ususally track what happened after I do my decision. Therefore my information about the subject gets old after some time.

 

[rguo]

My opinion is FPGA advantage is the counterpart to active hdl, which includes design entry, simulation and synthesis together by bundling hdl designer, model sim and leonardo, and also more powerful than active hdl.

rguo