Mod 6 3-Bit D-type asynchronous down counter design

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Hi

I am trying to design a Mod 6 3-Bit D-type asynchronous down counter using Pspice and I am having difficulty with the Nand gate in order to make the count go from 5-0. In its present state it is counting from 7-0 and I know with the addition of adding a NAND gate I can reduce the count to the desire 5-0 but I have no idea how to connect the gate up in Pspice. I have tried various positions but cannot get the desired output.

Can anybody help me out as to where to connect the gate? I have added an image of the construction so far.

 

You want to change the middle bit to 0 immediately when the readout is '111'.
It is sufficient to detect '11' in the MSB's. Send those bits to your logic gate.
Put a diode at its output. Point it in one direction or the other, whichever works.
Attach to the 'reset' (I think) of the middle bit.

You may find you need to add a pullup or pulldown resistor, with a sufficiently high ohm value so as to permit normal operation at all other times.

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As an alternate, does your LSB send an underflow when the count transitions from 000? Take advantage of that as a signal to change the middle bit to 0.
 

Hi Ive had a go at adding a gate to the 2nd and 3rd output (Reset= Not2.Not3). I would have thought that would have provided the signal to go back to reset and stop the count going beyond 5 but no dice it doesn't work. Any ideas?

 

Not exactly sure of the educational benefit of this kind of design except to point out how bad it glitches when you do asynchronous stuff like this.

The problem with the current version of your design is the RST pin of the middle FF is connected to the other two FFs and the output of the NAND. The only connection to the RST pin of the middle FF should be from the output of the NAND.
 

I have changed the reset pin but it is still not giving the desired count. Is there anything else I could try?

 

I had a feeling this change wouldn't work, all the glitches are probably causing an inadvertent reset of that center FF. You can see momentary high values (glitches) on the middle waveform.
 

Hi I am still no further forward are there any other suggestions I could try to get it working
 

Have you considered the race conditions inherent in ripple counters?

You need to find out when the reset is happening and see why the count is wrong.
 

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