MMCM Clocking Wizard

[Roronoa137]

I'm using the clocking wizard IP to generate three different clocks starting from an input clock.
These are the setting for the IP:

INPUT CLOCK:
Input Frequency: 12MHz
Input Jitter: 0.010
Source: Single ended clock capable pin

OUTPUT CLOCK:
clk_out1: 100 MHz
clk_out2: 300 MHz
clk_out3: 10 MHz
For all of them: phase=0, duty cycle=50%

If I take a look at the MMCM Settings, without enabling the "Allow Override Mode", what I have is:
CLKFBOUT_MULT_F = 50.000
CLKFBOUT_PHASE =0.000
CLKIN1_PERIOD = 83.333
CLKIN2_PERIOD = 10.0
DIVCLK_DIVIDE = 1

clk_out1: Divide=6.000
clk_out2: Divide=2
clk_out3: Divide=60

For the constraints:
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { clk_sys }]; #IO_L12P_T1_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clk_sys}];

If I run the simulation and check the waveform for the output clocks, they are not the ones expected, in details:
clk_sys: 12,195,121.95 Hz
clk_out1: 9,756,097.56 Hz
clk_out2: 29,268,863.78 Hz
clk_out3: 975,609.75 Hz

Can someone help me understanding what I'm doing in the wrong way? Thank you

 

[ads-ee]

clk_sys is 82 ns, which tells me that you are probably running in 1ns/1ns in the simulation as you are likely generating your testbench clock using 41.66 as the half period toggle time and the 1ns precision is truncating that down to 41.