mixing blocking and nonblocking statements

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rocking_vlsi

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sorry if it is repeating.

people does mix of both blocking and non-blocking statements.
as

always@(posedge(clk))
begin
temp_var=a&b;
if(condition)
temp_reg<=temp_var;
end

For simulation and synthesis how does it differ?
 

do it like this to separate the combinational and sequential code

Code: 
assign temp_var = a & b;

always@(posedge(clk))
begin
if(condition)
temp_reg<=temp_var;
end
 

What tariq said is conventional method, used widely. The point is if they are mixed: Now since order of execution for same activity constraint always block is random, in this case sometimes you may get race condition if blocks using temp_var are executed earlier than this. So if you are really forced to mix, make sure that temp_var is nor used elsewhere at posedge clk.
 
Last edited:

dave_59 said:
Definitely a race condition in simulation if temp_var is read on a p(osedge clk) in another block.
Click to expand...

Dave, correct me if i am wrong. Even if temp_var is read on posedge clk in another always block in a non-blocking assignment, the old value of temp_var will be sampled rather than the new one. For example

Code: 
//first always block
always@(posedge(clk))
begin
temp_var=a&b;
if(condition)
temp_reg<=temp_var;
end

//second always block
always@(posedge(clk))
begin
another_temp_reg<=temp_var;
end
 

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