Non AMP

Mixed Signal Vlsi Design

Thread starter somulu
Start date Jun 25, 2011

Status: Not open for further replies.

Jun 25, 2011

#1

S

somulu

Member level 1

Hai to all, I am searching for good material on Mixed Signal VLSI Design.Please if any body have good material attach it to gugulothusomulu06@gmail.

Jun 25, 2011

#2

L

ljxpjpjljx

Advanced Member level 3

ok, I will send you some material!

Jun 28, 2011

#3

S

somulu

Member level 1

ljxpjpjljx said:
ok, I will send you some material!

Sir please attach the material.

Status: Not open for further replies.

Similar threads

L
Question about creating a LIB timing files for a mixed-signal hard macro
- Started by lawfulgm
- Sep 3, 2024
- Replies: 7
ASIC Design Methodologies and Tools (Digital)
K
VCS Mixed Simulation VCS VHDL Verilog Mixed language simulation with UVM
- Started by Kashif Minhas
- Oct 8, 2024
- Replies: 6
ASIC Design Methodologies and Tools (Digital)
K
Unable to Dump VHDL Design Signals in VCD file Using VCS
- Started by Kashif Minhas
- Oct 22, 2024
- Replies: 2
ASIC Design Methodologies and Tools (Digital)
Q
System Verilog Design a signal flag.
- Started by quocviet19501
- Sep 19, 2023
- Replies: 4
ASIC Design Methodologies and Tools (Digital)
C
How to declare a define of verilog in design compiler?
- Started by coshy
- Dec 5, 2024
- Replies: 1
ASIC Design Methodologies and Tools (Digital)