Mix auto and manual P&R (in Cadence Encounter)

[Alosevskoy]

Hi! I'm new to Cadence Encounter.
Let's consider a hierarchical design consisting of two modules - the top module TMod and the submodule SMod - both of them are verilog netlists.
TMod contains some logic and an instance of SMod - inst_SMod.
I want to do manual place & route for block inst_SMod. Place & route for TMod's cells should be made automaticly by program. inst_SMod's cells should not be placed in the particular area, instead they are should be spreded around the whole core area and for placing & routing of TMod's cells program uses the rest space of the core area.
I tried the next steps:
- I wrote DEF file for inst_SMod which contains p&r information (cell's locations and routing metal shapes).
- in Encounter: (i) Import Design (with TMod as the top module), (ii) Floorplan, (iii) Power Planning + SRoute, (iv) Auto Placement of std. cells (TMod's cells & inst_SMod's cells), (v) Load DEF file for inst_SMod, all looks great...
- but when I do automatic tracing (with Nanoroute) TMod's cells do not want to connect to inst_SMod's cells. I think tracer doesn't understand how to trace because it can't see pins? on inst_SMod's metal layers which are inputs and outputs of this block.
So... how to place these pins? Or may be the way is initially wrong?

I would be very thankful if you could advise me the way to solve this problem.
Thank you!

Alexander

 

[GI]

Dear Alosevskoy,

You can behave Smod as a block. I'm assuming that you're doing your manual work in SOC Encounter.

01 - During manual work of Smod, you need to create pins and place them at block boundary.
02 - Then you need to instantiate Smod inside Tmod netlist and import this netlist into PR tool, so that PR tool will be aware of the connectivity information.
03 - Then the router should be able to route to pins of Smod.

You can also use partitioning flow in SOC encounter. For this flow, you can read in whole netlist including Smod first and make partition the top level into desired level of hierarchies for easier Place & Route.

BR,
Gokhan
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[Alosevskoy]

Gokhan, thanks for you reply! I tried to follow the steps described above (without using partioning). But I have met some problems.
In step 01: Yes, I can do complete PR for Smod block. After that I save PR results into Smod.DEF file. To make hier path for Smod nets/pins/cells to be correct I edit some strings in Smod.DEF (Ones again - I do this because when I do PR Smod is top module and now it becomes submodule for Tmod):
For example i replace
- i_inv IVLL + FIXED ( 33920 8960 ) N
with
- Smod/i_inv IVLL + FIXED ( 33920 8960 ) N
In step 02: I import hier verilog netlist into Encounter (Tmod with instantiated Smod in it). Now I can load Smod.DEF file. Relative locations of Smod's cells and routing are ok. I can select all the elements of Smod block and move them to the place I wish. The problem is I don't see Smod pins. Log file keeps some information about what's happened:
Reading DEF file 'Smod.def', current time is Mon Oct 31 18:23:17 2011 ...
--- DIVIDERCHAR '/'
--- UnitsPerDBU = 1.0000
**WARN: (ENCDF-244): Pin 'c_a' is not created because it's not in the netlist and also not a P/G pin.
**WARN: (ENCDF-244): Pin 'c_b' is not created because it's not in the netlist and also not a P/G pin.
**WARN: (ENCDF-244): Pin 'c_out' is not created because it's not in the netlist and also not a P/G pin.
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
Extracting macro/IO cell pins and blockage ......
Pin and blockage extraction finished
DEF file 'Smod.def' is parsed, current time is Mon Oct 31 18:23:17 2011.
I think problem with hier paths for pins in Smod.DEF file...

My next step is placing other std cells (Tmod cells)... No problem.
When I execute Nanoroute it doesn't want to route to Smod, I think because of the problem with pins described above ..

Alexander

 

[GI]

Dear Alosevskoy,

Apologies for the late reply. I guess you already completed the design, if not here is my answer:

From the log file you've shared the problem seems to be pins that are not created in verilog file.

1. For signal pins you need to have pins for Smod pins inside the verilog file, to match the pins in def file.
- In your situation, there seems to be a discrepancy between def file & verilog file. For example for the line "**WARN: (ENCDF-244): Pin 'c_a' is not created because it's not in the netlist and also not a P/G pin.", it says that "c_a" pin does not exists in verilog, and also it is not declared as a power pin in P&R tool. YOu either need to declare it as a power pin (if it is so), or add it to verilog.

2. For power pins, you don't need to have them in verilog. YOu can directly create them in place and route tool.

I hope it helps,
BR,
Gökhan
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