misunderstanding vhdl process?

  myVJtagInstance : MyVJtag port map (
    ir_out => ir_outB,
    ir_in  => ir_inB,
    tdi => tdiB,
    tdo => tdo,
    tck => tck,
--    tms => tms,
--    virtual_state_cdr  => led(0),
--    virtual_state_cir  => led(1),
--    virtual_state_e1dr => led(2),//0
--    virtual_state_e2dr => led(3),
--    virtual_state_pdr  => led(4),
    virtual_state_sdr  => sdr--led(5),//0
--    virtual_state_udr  => led(6),
--    virtual_state_uir  => led(7)
    );

load1 <= ir_inB(0) and not(ir_inB(1));
  --load2 <= ir_inB(1) and not(ir_inB(0));
  --comp  <= not(ir_inB(1)) and not(ir_inB(1));
  --store <= ir_inB(0) and ir_inB(0);

  --statusOk <= tdi='1' or tdi='0';

  readArg1 : process (tck)
    begin
      if rising_edge(tck) then 
        if load1='1' and sdr = '1' then 
          arg1(7 downto 1) <= arg1(6 downto 0);
          arg1(0) <= '1';--tdiB; -- shift
        end if;
      end if;
    end process readArg1;

 led <= std_logic_vector(arg1);