EmbdASIC
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I have a four stage amplifier, which is very sensitive to mismatch variations. That is surely visible by my monte carlo (process + mismatch) simulations.
Apparantly a 1% mismatch in input differential pair shifts the DC points to such a level that some transistors in the later stage leave saturation region, which is the reason for bad results in monte carlo sims.
A scaled size W/L does not control this mismatch problem, and i want to know how to optimize this circuit to make it more prone to mismatch variations.
Looking forward for some good suggestions.
Regards,
EA
Apparantly a 1% mismatch in input differential pair shifts the DC points to such a level that some transistors in the later stage leave saturation region, which is the reason for bad results in monte carlo sims.
A scaled size W/L does not control this mismatch problem, and i want to know how to optimize this circuit to make it more prone to mismatch variations.
Looking forward for some good suggestions.
Regards,
EA