sarjumaharaj
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Hello,
I am trying to implement a single cycle MIPS processor. I've been able to execute the dual level controller but there seems to be some error with the datapath. Can someone please see and tell me what the error is.
I used a test output signal called test_pc to check if the value from pc is correct or not. Initially 0's and then incremented by 4 after each clock cycle. However, the value of PC doesn't seem to be set. XXXXX is displayed in the output waveform. What is the reason for this.
Also, this MIPS processor doesn't handle jump instructions. Just R and BEq and sw lw
CODE FOR DATAPATH:
Code for PC:
I am trying to implement a single cycle MIPS processor. I've been able to execute the dual level controller but there seems to be some error with the datapath. Can someone please see and tell me what the error is.
I used a test output signal called test_pc to check if the value from pc is correct or not. Initially 0's and then incremented by 4 after each clock cycle. However, the value of PC doesn't seem to be set. XXXXX is displayed in the output waveform. What is the reason for this.
Also, this MIPS processor doesn't handle jump instructions. Just R and BEq and sw lw
CODE FOR DATAPATH:
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:24:19 05/06/2014
-- Design Name:
-- Module Name: datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity datapath is
port (
clk : in std_logic ;
regwrite , RegDst,ALUSrc , MemWrite ,MemRead , MemtoReg , PCSrc : in std_logic ;
aluCtrl : in std_logic_vector (2 downto 0 ) ;
funct : out std_logic_vector ( 5 downto 0 ) ;
opcode : out std_logic_vector ( 5 downto 0 ) ;
test_pc : out std_logic_vector (31 downto 0)
);
end datapath;
architecture Behavioral of datapath is
component instreg is
port ( clk : in std_logic ;
pc : in std_logic_vector (31 downto 0 ) ;
instruct : out std_logic_vector (31 downto 0 )
);
end component;
component PC is
port (clk : in std_logic;
pc_in : in std_logic_vector (31 downto 0);
pc_out :out std_logic_vector (31 downto 0 ) );
end component;
component reg_in_mux is
port (ld_sig : in std_logic ;
ad_add , ad_ld : in std_logic_vector ( 4 downto 0) ;
ad_out : out std_logic_vector ( 4 downto 0)
);
end component;
component registerfile is
port ( clk , regw : in std_logic ;
rad1 , rad2 , wad : in std_logic_vector (4 downto 0) ;
data_in : in std_logic_vector (31 downto 0);
rd1 : out std_logic_vector (31 downto 0) ;
rd2 : out std_logic_vector (31 downto 0)
-- test : out std_logic_vector (31 downto 0)
);
end component;
component reg_out_mux is
port ( add_sig: in std_logic ;
reg_data , sx_data : in std_logic_vector (31 downto 0);
mux_out : out std_logic_vector (31 downto 0)
);
end component;
component sign_extend is
port ( offset : in std_logic_vector ( 15 downto 0 ) ;
offset_out : out std_logic_vector ( 31 downto 0 )
-- msb_check : out std_logic
);
end component;
component alu1 is
port (rd1 , mux_op :in std_logic_vector (31 downto 0);
op : in std_logic_vector (2 downto 0);
alu_out : out std_logic_vector (31 downto 0 );
z : out std_logic ;
slt : out std_logic );
end component;
component data_memory is
port ( clk , rd , wrt : in std_logic ;
address : in std_logic_vector (31 downto 0 );
data_in : in std_logic_vector (31 downto 0) ;
data_out : out std_logic_vector (31 downto 0)
);
end component;
component datamemo_mux is
port ( memtoreg: in std_logic ;
dm_data ,alu_data :in std_logic_vector (31 downto 0) ;
to_reg : out std_logic_vector (31 downto 0 )
);
end component;
component pc_adder_block is
port ( pc_memo : in std_logic_vector (31 downto 0) ;
to_pc : out std_logic_vector (31 downto 0) );
end component;
component shifttwobits is
port ( offset : in std_logic_vector (31 downto 0 ) ;
out_offset : out std_logic_vector ( 31 downto 0 ) );
end component;
component shift_two_bits is
port (ad1 : in std_logic_vector ( 31 downto 0 );
ad2 : in std_logic_vector (31 downto 0) ;
out_ad : out std_logic_vector ( 31 downto 0)
);
end component;
component alu32_mux is
port ( branch : in std_logic;
normal , beq : in std_logic_vector (31 downto 0 ) ;
toPc: out std_logic_vector (31 downto 0 )
);
end component;
component andgate is
port ( a , b : in std_logic ;
c: out std_logic );
end component;
signal sig_pc_in ,sig_pc_out : std_logic_vector (31 downto 0 ) ;-- pc signal
signal sig_inst : std_logic_vector (31 downto 0 ); -- instruction memory signal
signal sig_funct, sig_opcode : std_logic_vector (5 downto 0);
signal sig_rs ,sig_rt , sig_rd : std_logic_vector (4 downto 0);
signal sig_offset : std_logic_vector (15 downto 0);
signal sig_wad : std_logic_vector (4 downto 0);
signal sig_dataToReg : std_logic_vector ( 31 downto 0);
signal sig_rd1 , sig_rd2 : std_logic_vector ( 31 downto 0 ); -- this one is register data
signal sig_sx : std_logic_vector (31 downto 0);
signal sig_dataAdd: std_logic_vector (31 downto 0);
signal sig_z , sig_slt : std_logic ;
signal sig_aluOut : std_logic_vector (31 downto 0);
signal sig_DM_out : std_logic_vector (31 downto 0 );
signal sig_PCadrOut : std_logic_vector (31 downto 0 );
signal sig_shifted : std_logic_vector (31 downto 0);
signal sig_shiftAdd : std_logic_vector (31 downto 0 );
signal sig_branch : std_logic;
--signal sig_DMMuxOut : std_logic_vector (31 downto 0);
begin
pcwala: pc port map (clk ,sig_pc_in , sig_pc_out);
instructionmemory: instreg port map ( clk , sig_pc_out , sig_inst );
--dividng the various components of the instruction fetched from IM
sig_opcode <= sig_inst ( 31 downto 26);
sig_rs <= sig_inst ( 25 downto 21); --in the book rd is the destination here rd is the source rt is the destination
sig_rd <= sig_inst (20 downto 16); -- this one is rs rd rt wala rd
sig_rt <= sig_inst (15 downto 11);
sig_offset<= sig_inst (15 downto 0);
sig_funct <= sig_inst (5 downto 0);
loadmux: reg_in_mux port map (RegDst , sig_rt , sig_rd, sig_wad );
regfile : registerfile port map ( clk , RegWrite, sig_rs , sig_rd , sig_wad , sig_dataToReg , sig_rd1 , sig_rd2 );
storemux : reg_out_mux port map ( ALUSrc , sig_rd2 , sig_sx , sig_dataAdd);
signextender: sign_extend port map (sig_offset , sig_sx );
ALU_conn : alu1 port map ( sig_rd1 , sig_dataAdd , aluCtrl , sig_aluOut , sig_z ,sig_slt);
datamemory : data_memory port map ( clk , MemRead, MemWrite , sig_aluOut, sig_rd2 , sig_DM_out );
datamemoryMUX : datamemo_mux port map ( MemtoReg , sig_DM_out , sig_aluOut , sig_dataToReg);
PCplusfour : pc_adder_block port map (sig_pc_out ,sig_PCadrOut ) ;
shifter : shifttwobits port map ( sig_sx ,sig_shifted);
addAfterShift_BEQ: shift_two_bits port map ( sig_PCadrOut , sig_shifted , sig_shiftAdd ) ;
BranchMUX: alu32_mux port map (sig_branch , sig_PCadrOut ,sig_shiftAdd , sig_pc_in ) ;
andgater : andgate port map (PCSrc , sig_z, sig_branch) ;
funct <= sig_funct ;
opcode <= sig_opcode;
test_pc <= sig_pc_out;
end Behavioral;Code for PC:
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:38 05/09/2014
-- Design Name:
-- Module Name: PC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC is
port (clk : in std_logic;
pc_in : in std_logic_vector (31 downto 0);
pc_out :out std_logic_vector (31 downto 0 ) );
end PC;
architecture Behavioral of PC is
signal sig_internal: std_logic_vector (31 downto 0):= (others => '0') ;
begin
process ( clk , pc_in )
begin
sig_internal <= pc_in ;
if (rising_edge(clk)) then
pc_out <= sig_internal ;
end if;
end process ;
end Behavioral;