minimum reset pulse requirement

[Ahmed_elshaer]

Is there a minimum reset pulse width requirement for the flip flop?
Also, what happens if the reset input of a reset synchronizer glitches while the clock qas off for sometime (and will remain off for sometime)? will the reset synchronizer output be asserted? or remain de-assertes? or goes metastable?

 

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Is there a minimum reset pulse width requirement for the flip flop?
Also, what happens if the reset input of a reset synchronizer glitches while the clock qas off for sometime (and will remain off for sometime)? will the reset synchronizer output be asserted? or remain de-assertes? or goes metastable?

there is always a minimum reset pulse width requirement and you find it in the documentation that exists for the technology library you are using.

if the reset glitch exceeds the pulse width requirement then it will cause a reset to occur that will not be (synchronously) deasserted as their is no clock running. If the pulse width isn't exceeded then the results are indeterminate.

Basically you should ensure that the reset input doesn't glitch, which is why designs I've worked on have low pass filtering on the reset input of the ASIC/FPGA.