Minimum peak detector

[Kunna]

I need to detect the minimum peak of a sawtooth signal and output it. Does anyone have an idea how i could do that?
EDIT:Maybe i should clarify, using CMOS circuit design.

 

[chuckey]

Interesting little waveform Is there anything else you can tell us about when this "little" sawtooth occurs? i.e. is it completely at random? I can not see how we can detect the difference between the most negative excursions of the big saw tooth and the little sawtooth.
Frank

 

[Kunna]

Interesting little waveform Is there anything else you can tell us about when this "little" sawtooth occurs? i.e. is it completely at random? I can not see how we can detect the difference between the most negative excursions of the big saw tooth and the little sawtooth.
Frank

I have converted Pulse width into an amplitude(that is what u see there, the max always occurs on the falling edge of that PWM). So getting the minimum peak will give me the smallest pulse width. I've thought about use a CMOS latch storing those peaks and then using a comperator to find out what the smallest one is. But a latch is digital, and if my +VCC is 3.3v and -VCC the GND ( so binary 1=3.3v and 0=0v) and i want to store lets say 1.3v won't the latch converge that value to a binary 0, which equals to 0v. Meaning i have lost my input.

 

[Prototyp_V1.0]

Hi.

Since you seem to compare it against later "waves", you need to have a function that remember many peaks and that can compare them. Ie, you need some microcontroller.

 

[Kunna]

Hi.

Since you seem to compare it against later "waves", you need to have a function that remember many peaks and that can compare them. Ie, you need some microcontroller.

cant use microcontoller its IC.
Seems like a though question...

 

[Prototyp_V1.0]

cant use microcontoller its IC.
Seems like a though question...

Yes, but how do you make the circuit to "know" the next pulse?

Anyway, you have to make at least two storage circuits (sample and hold), probably more.

 

[zorro]

The falling edge of the pulse (that is used for reset of the integrator) can be used for storing its voltage into a sample-and-hold circuit, only if the new value is lower than the old. I.e., there is a comparator that enables or not the S&H. (There should be a small delay before the integrator reset.)
Regards

Z

 

[E-design]

I would have expected the sampling waveform to look different with at least some dead time between samples. I don't see it in your waveform. Am I missing something?

 

[Kunna]

I would have expected the sampling waveform to look different with at least some dead time between samples. I don't see it in your waveform. Am I missing something?

Yeah u are right, there should be dead time in between. The drawing i made is just bad :S