minimum oxide thickness to avoid gate tunneling in NMOS?

[just doit]

hi,
I am working on NMOS device modeling, I am getting confused with the thickness of gate oxide. what is the minimum approximate gate oxide thickness to avoid gate tunneling (gate leakage) in a mosfet.
If i want to design a 16nm gate length NMOS, then what is the appropriate gate oxide thickness i have to take to avoid gate tunneling.

any suggetions are appreciated.
Thanks in advance.

 

[dick_freebird]

Tunneling happens. You want to look at the applied voltage
and the "oxide" quality & composition, to decide on a Tox.
You also may elect to tolerate some tunneling, based on
whether or not you see damage or intolerable gate current;
maybe some other reliability effect is more important in the
end.

Especially in high-K dielectrics, which are thinner and of
poorer quality, I see thing like a nitride final layer to get
the insulation. Then you're into heterogenous strangeness
as far as the physics.