Minimum output voltage for this diode connected differential pair

[MahmoudHassan]

For the Circuit shown in figure 1 it is required to know the minimum allowable output voltage

for fig 2 it is the instructor solution for it

as there is two constraints or possibility
the first one M1 at the edge of triode region
and so vout1,2 Min = Vss + VDS1 and as m1 at the edge of triode region VDS1 = VGS1-Vthn so Voutmin can be calculated

the other possibility (the one i am not understand )
When all of ISS pass through M3 when this can happen and why this may happen ?
the first and second constraint solution is shown in fig 2

(This problem number is 4.14 in Design of Analog CMOS integrated circuti by B.Razavi page 130 and solution in page 107 in instructors solution manual )

 

[y.gh]

hi,
if vin>25mv then M1 is in saturation area and M2 is cut off so all ISS goes to M3(&M1)
ok?

 

[MahmoudHassan]

mmm , actually i didn't understand your answer can you provide me more details (honestly it is not a home work assignment )

 

[y.gh]

when u use in large signal,one side of u'r amplifier works.so, all of current goes to one side.in large signal mode one of M1 or M3 is ON and another is OFF.