Minimum AMBA AXI frequency

Hi friends,

I just wants to know the minimum AMBA AXI frequency at which the protocol working properly.

Is anyone know please replay.

Thanks in Advance

Given that 90nm AXI implementations can likely achieve frequencies over 400MHz, the bandwidth available for a 128-bit AXI implementation is 12.8GB/s. AXI does not have the number or variety of IP cores available on AHB, however it is likely that only high performance cores will be designed to AXI, and that low to mid-performance legacy AHB cores will be accessed from AXI through a bridge. AXI is supported by a wide range of verification IP that supports many different languages and environments.

---------- Post added at 18:26 ---------- Previous post was at 18:23 ----------

I think this should be very helpful to you.. unable to attach from my office network, but download it,

http://www.power.org/resources/downloads/Embedded_Bus_Arch_Report_1.0.pdf

Thank you for your replay, but the thing i wanted is the MINIMUM AMBA AXI frequency.

Why i am looking the minimum frequency is nothing but to know.

frequency is not a parameter that is dependent on crystal... its usually user configurable depending on various parameters.

Address and data bus width are configurable. For AMBA and CoreConnect data bus width depends on type of the bus (for
AHB and ASB bus width is 32, 64, 128 or 256 byte, for APB 8, 16 or 32 byte and for PLB bus width is 32, 64, 128 or 256
byte, for OPB 8, 16 or 32 byte and for DCR 32 byte).

AMBA 2 AHB synthesizes to 200 MHz at 90 nm process. For 32-bit data, peak system bandwidth is 32 * 200 = 6.4
AMBA 3 AXI synthesizes to 400 MHz in a typical 90 nm process. The peak bandwidth is 400 MHz * 32 bits = 12.8 Gbps

Operating frequency is for all buses user defined.
CoreConnect defines maximum frequency depending on the PLB width (for 32 b PLB width maximal frequency is 256
MB/s, for 64 b PLB width 800 MB/s and for 128 b PLB width, 2.9 GB/s)

Thanks a lot Mr.Shivaram