Min, Max, Typical violation in GLS

[Ben_Beckman]

What are some of the major reasons for causing timing violations while doing gate level simulation?

 

[ranaya]

What are some of the major reasons for causing timing violations while doing gate level simulation?

If the design is over-clocked during GLS, you violate setup time. The hold violations are fixed at the post layout stage. So if not for the first case, you might be seeing hold violations...