Milliken's capless LDO technique

hi,

has anybody implemented Milliken's capless LDO technique? (other than milliken

if yes, how does it work? any complications? points that i should take care?

thanks in advance.

regards,
JT

capless regulator

Hi jt_rf,

I haven't tried out the design.
But, since I also do LDO for my project, I would like to share my understanding about LDO. Please correct me if I'm wrong. =)

In a three-stage LDO (i.e. two stages of error amp and one stage of pass transistor), there are at least 3 poles exist. One is at the LDO's output, the other two are at the output of each stage of error amp. Assuming that the output cap is very small, which may be true since you said about capless LDO, we can say that the three poles location is quite near. In order to achieve stability, you need to:
1. push one of the pole to lower freq and push the others to higher freq, or
2. in addition to step 1, add LHP zero to increase the stability even more.

There are many techniques to push the pole to lower frequency. The most famous one is by using Miller compensation, which is based on pole splitting technique. The problem with this technique is the existence of RHP zero, which is unwanted. To eliminate this RHP zero, many method has been proposed, e.g. using nulling resistor, feedforward stage, voltage buffer, current buffer, current mirror, cascode compensation (enhanced method of current buffer). Some of these technique even can introduce LHP zero.

One of the problem in LDO is due to its changing load resistance. In conventional LDO, people create a dominant pole using this changing load resistance and a very big output cap. The problem occurs when RL is very small (due to the heavy load current). At this time, the dominant pole shifts to higher frequency, causing the non-dominant poles to be located inside the UGF. Thus, ESR zero was used to compensate the LDO. However, this technique requires a very big cap and specific range of ESR, which makes this compensation a bit troubelsome and not suitable for SoC.

Nowadays, people very seldomly make use of the output pole as the dominant one. They usually create a dominant pole by using the enhanced Miller compensation, which has been discussed earlier. To compensate the changing pole, some people try to lower the UGF and use a constant zero to compensate it when it comes near the UGF. Other researchers proposed to use a dynamic zero, which is able to change its location according to the load current. The problem with this technique is that, it cannot accurately track the load pole, because it is only able to track the load current, but not the load capacitance. However, it is still much better than just a constant zero.

For the dynamic zero, you can look at this paper:
- Pole-zero tracking frequency compensation for low dropout regulator
- A Low-dropout Regulator with Unconditional Stability and Low Quiescent Current

I think that's my brief introduction about LDO. Hope it can help. =)
For the reader of this post, please correct me if I'm wrong.
Thanks a lot! =)

capless ldo

can you post the papers?

capless ldo regulator

can you post the papers?

milliken ldo

You can look at this link:



and here is the other:

ldo dynamic load

Hi Jt_rf,

I have implemented the Milliken's LDO. Good thing about the design is that it works with the stated boundries. The problem occurs when you simulate
it for corner cases. Typical case it works quite fine ..

Raduga

capless ldo tamu

Dear Raduga,

thats good. what problems did you face in the corners? is it the transient response problem with stability? if we introduce some programmable resistance or capacitance, cant we solve it over the corners?
anyways, thanks for the earlier reply.

regards,
JT.

ldo changing load

Hi JT,

The problem is that when your LDO is in the No-Load
condition and the corner you have low Vt for pass device

it will pull the load transistor of your error amp in
linear region which will screw the loop-gain totally

also, the jucture where your error amp and differentiator
is connected that is a tricky to size ...

Regards
Raduga

voltage regulator capless

Thanks Raduga. Thanks for your inputs.

capless ldos

good

capf-less regulator

I thinks so, but I think it is impossible to design a capless LDO with a heavy load.

milliken regulator

That design is not entirely capless .. it has a load cap of 100pF .. but the dominant pole in this case is
the internal pole i.e. at the o/p of error amp..

Raduga

differentiator fast loop ldo

one thing, that is not clear to me is:

what is the general solution for some applications that are capless LDO's with load currents less than 5mA but serving Analog/RF applications. Their transient load regulation spec will be tight. we cant increase the Iq bcos load current itself is less, other way is to introduce the fast transient loop, like thesis of Milliken, but that fails at corners!!

cap less ldo

Attached please find the paperole-zero tracking frequency compensation for Low Dropout Regulator.

millikens capless ldo

jt_rf, for your question, maybe the only way to fit the tight spec is to increase the loop transient response, but it always means to increase Iq, for low Iq LDOs, it is very tough tasks to have fast response.

For example, 100uA for a 5mA loaded LDO sounds reasonable. and 100uA maybe enough to fast a loop.

site:edaboard.com capless ldo

In my opinion, Milliken's structure introduces big variation according to mismatch. It will not suit for practical application. As I remembered, an external reference is used in his paper. For LDO product, internal reference should be must. The mismatching problem will be obvious.

capless low dropout regulator

shouldn't the pole at the output dominated by the pass transistor resistance other than the load resistance, why will the pole created by adding a big cap at the output move with load current?

ldo rf soc thesis

Hi,
One question about the capless LDO? Does it mean it can work only without cap? I don't think it will be the case since some pass transistors will always be added to enhance the transient repsonse, say spike or dip, in such case, is it possible to develop a LDO that is adaptive to all cap? Looks quite impossible. Someone proposed to shift the dominant pole to the internal, but will that survive with any cap, especially at no load? Even that we can introduce a zero in internal circuit, how much space will it cost?

capless_ldo

For a pfet pass device, vdropout is its vdsat.
Is this also the same for the nfet device design ? Also assuming that the parasitic Cgs and Cgd can be handled properly, what is the minimum Vdropout that a real life design can achieve in today's CMOS technology ?

Thanks,

dbmd

capless ldo thesis

Bumped for reponse. Thanks.