Miller's problem in P channel MOSFET

Turnoff drive is much too weak and the NPN can't get you to
zero Vgs.

Show your probing / prototype setup, a picture or two.

A sim :




Good probing techniques : https://download.tek.com/document/02_ABCs-of-Probes-Primer.pdf


Regards, Dana.

Hi,

azadfalah said:

I designed a p-channel MOSFET driver,

Click to expand...

May I ask: why?
In decades of electronics design I never got the idea to design one on my own.

There are ready to buy drivers. With much better performance than yours, smaller, and often with additional features.

******
But the circuit above isn't well designed. I miss capacitors to stabilize the voltage ... by cancelling out stray inductance.
And this is what I expect to be the problem with your circuit. And it's not only the schematic, but also the PCB layout that determines the performance.
The key to success:
* low impedance
* stable supplies
* short wiring
* stable reference

Klaus

If you turn on the lower mosfet too fast - the dv/dt seen by the upper mosfet puts a capacitive current into the gate and turns it on - this is covered in the literature

So either a better gate drive with lower Z at these high freq edges - or use a 33 ohm turn on resistor ( in the bottom fet and the top fet ) and a reverse shottky to give good turn off ....

- you're welcome

Thanks Easy peasy, did not know about this effect.




Regards, Dana.

Easy peasy said:

So either a better gate drive with lower Z at these high freq edges - or use a 33 ohm turn on resistor ( in the bottom fet and the top fet ) and a reverse shottky to give good turn off ....

Click to expand...

Thanks Easy peasy, With 56 Ohm gate resistor and reverse shottky for quick shutdown






According to the results, I have to work on increasing the current of the driver, do you have any suggestions to increase the driver whose schematic is in the first post?

Thank

It's a really crappy driver and you should throw it out for
a more capable, cleaner solution. It's quite likely that an
integrated MOSFET driver exists which will be lower BOM
cost than your handful of discretes and passives, not to
mention much better performing.

You need R4 to be much smaller if you mean to stick with
this bodge. Cds of Q5 with R4 makes a time constant that
must be lower than the Q5 drain fall time, a fair bit, to keep
Q5 "off". The Q4 "booster" may be uselessly weak relative
to Q5 Cgg if it's a small signal device. In any case it's not
likely to get you to Vgs=0 and at Vgs=1, maybe your FET
conduction is problematic (subthreshold leakage on a 10A
FET may still be tens, hundreds of mA).

Be sure you look at -loaded- driver behavior as this will mellow
out the PFET's drain risetime. Don't use a larger FET than
conduction loss budget demands.

the zener should go to Q1 emitter, with a fixed resistor to gnd to get say 8mA in the zener, then add 220nF across the zener to stiffen up the supply,

then the pull up to Q4,Q1 base can be a pnp current source, which is pulled low by Q7 - rated for full rail volts ( you can now short R57 as the current is limited )

add a schottky diode collector to base ( kathode ) to stop this junc becoming forward biased under turn on.

Other, better designs can be considered also

Driver application notes :



Note there are a ton of integrated drivers with additional features and capabilities should you
choose that route.



Regards, Dana.