Miller compensation at low voltages

[opamp741]

Hi frds,
I m doing a 2 stage amp design at 1.1V..I m using miller comp tech for getting a PM of around 65..
but the implementation of Nulling resistor is a big issue for me rgt now..I m implementing it by transistor and generating the resistor Bias (RB) so that it tracks the Gm of the 2nd stage input transistor. but the problem is lower supply voltage, i m unable to get proper VDS for current source in RB generation ckt ..Can anybody suggest me any other method for generating RB..

 

[steer]

There is no way to generate right RB voltage, unless you resort to bootstrap.
My proposal is to go a way around, that is put a resistor for zero and derive bias current for the op-amp from the same kind of resistor to match transistors gms to the resistor.

 

[Vamsi Mocherla]

Actually, If the area is not a major concern, you can bias the transistor with VDD and hence make it work in the linear region. You can control the W/L s to get the resistor value by 1/gm. This is OK for high frequency but the transistor will be very big for low frequency operation

 

[opamp741]

thanx buddies..
steer, ur suggestion looks intresting..i will look at it in detail..
vamsi, i already tried the thing u suggested..but i was not able to make a good PM in all corners..

 

[lastdance]

to cancel the feedforward zero, there are a few other techniques, including buffering around the miller feedback. Refer to Gray and Meyer's book.

 

[Vamsi Mocherla]

Opamp741.....When you start designing for that, you should have the owrst corner in mind to design for better PM. So, you will get good results in the typical case

Added after 54 seconds:

Also, you can try buffering and introduce some poles in that loop. That will cause zeros in the LHP in the main loop

 

[opamp741]

Vamsi, tt is always fine for me..but i m not getting good PM for both ff and ss..It is like if i m making my zero too close in ss, its coming inside the UGB for ff and increasing my Gain cross over and i m getting lower PM..in other hand if i m setting my zero for ff then in ss its going away and again my PM is bad..

lastdance, i m working for a low power soln ..cant afford to put more current consuming branches..

thanx for ur FBs[/code]

 

[lastdance]

u can try this, cascode your p-input pairs (assuming u r using p diff pair), and then tie the Miller cap to the source of the cascode. The drain of the cascode would be used to drive the gate of the common source.

 

[opamp741]

lastdance, sorry to say but i already tried that..
and i'm really messed up by complex poles..they r coming very close to UGB..
infact we saw some stability issues in the inner loop also (second stage input xsistor-compensation capacitor-1st stage cascode xsistor)..
anyway, thanx for the reply..

 

[steer]

opamp741, yeah, I see what you're saying. If you go to cascode-fed compensation, in most cases it's necessary to split the compensation cap into two, one goes over cascode while the other goes across the output stage directly. This helps to avoid instability.
But wait, what is the relation between your 1st and 2nd stage gm's? If you make your input stage very weak, you can get good phase margin without any zero resistor in compensation at all.