MII to AXI4 interface

Hi,

I want to implement UDP communication on my FPGA board. There is PHY layer, chip wit MII interface. Common approach in UDP/IP stacks for FPGA is AXI4 interface to lower layers. Even Xilinx has IPcores for MII to AXI4 interfacing.

In MII are signals:

RXD[3..0] - data
RXDV - RX_Data Valid,
COL - Collision Detect,
CRS - Carrier Sense,
RXER - Receive Error,
RXCLK - Receive clock.

But in AXI4 is a signal which indicates about last byte of the received frame, asserted in parallel with that last data byte.

I can't figure out how to generate such a signal when I have only RXDV which is deasserted when data is finished, one clock step too late.

I could check the type of packet and e.g. from UDP packets get the 'length' parameter, but e.g. ARP packets don't have 'length' parameter. Additionally real packet recognition is created in higher layers, it should be only interface.

Anyone knows the subject and can help with this?

EDIT:
Or maybe someone understands Verilog and can read this code, because I see that 'Rx_m ac_eop' signal is what I need:
https://opencores.org/project,ethernet_tri_mode

Hi,
MII is a standard interface between the PHY later and the MAC layer. AXI4 is usually for processor and peripheral interface. So basically you can't direct convert AXI to MII. you need the MAC later integrated in your system, which the link you post is a MAC controller.

To be clear:
1. I have PHY layer chip which provide MII interface signals.
2. It is possible to get UDP/IP stack from opencores.org (https://opencores.org/project,udp_ip_stack) - it uses AXI interface to lower layer.
3. To connect 1. and 2. I could take
a) Xilinx Tri-Mode Ethernet Media Access Controller, but it is licensed -> $$$,
b) controller, which the link I've posted (https://opencores.org/project,ethernet_tri_mode), but it is in Verilog and I don't understand Verilog

I wanted to write it myself, because of 3a and 3b. It shouldn't be hard, but I don't understand one thing described in my initial post. How to get DATA_BYTE_LAST flag in parallel with that last data byte? This signal is required for AXI.
From MII I have information about data valid - RXDV and this is 'high' to the end of data frame and then go to 'low', so I can tell that DATA_BYTE_LAST was in previous clock cycle but not during the last data byte transmission -> in other words I can set flag that data frame is finished just after last byte of data frame.

if i'm not mistaken, my understanding from your post is that you are trying to build a bridge for AXI to MII so that you can directly connect the UDP/IP stack from open core to your PHY directly which is your point 2. I don't think it is possible as the MAC layer does quiet a number of tasks such as CRC, frame encapsulation, flow control and etc.

I would recommend you do the connection below:
UDP/IP stack (AXI) - AXI to MAC interface bridge - (user interface)open core MAC (MII) - PHY

As for the AXI to mac interface bridge, you can refer to MAC opencore documentation page 26 and 27 where they show the MAC user interface waveform. the interface do provide tx/rx_mac_sop and tx/rx_mac_eop to indicate frame start of frame and end of frame and tx/rx_mac_BE to indicate byte enable to tell which byte are valid.