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Mid-range mixed-signal IC design tools

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cascode

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We are a small company with a small group (2) of analog IC designer. So far, most of our designs have been mostly analog (up to50/50 Analog/Digital), relatively small chips. We have been using what would be referred to as ’low-end design tools’: Pspsice (for its mixed-signal capability), and Tanner Ledit for layout. Tanner is OK as a layout tool, but has some limitations, and no really integrated front-to-back capabilities. Pspice has some convergence issues, particularly with larger circuit, and limited digital design options.

We are looking at upgrading our tools to have more capabilities for more complex Mixed-Signal IC’s. Unfortunately, upgrading to one of the major vendor design suites is not an option due to $$$$$ limitations. We are likely to remain a small design team, so the big $$$ tools are hard to justify, and we do not get the benefit of saving much on the more expensive tools (ex.: verification, or fancy SOC simulator), that are usually shared among a larger group of designers.

For simulation, we are considering Dolphin’s Smash, as it seems too be a capable tool for mixed-signal, mixed-level simulations, and at a good price/performance ratio. Actually, it seems that all the other tools with similar capabilities are quite a bit more expensive.

For the rest, Paragon looks like a good option; Silvaco may also be one (may get a little more pricey).

I imagine there must be quite a few people struggling with the same dilemma?

If anyone has any recommendation, or experience with the ‘mid-range’ tools, I would greatly appreciate their comments.
 

Have you tried EverCAD's ADiT?
 

Perhaps you can consider the H$im, which has better performance on mixed signal simulation. However, I am not sure about the price.
 

If your are faced with the issue delivering an IP to an SOC integrator which contain A/D and you could not copy the multi-million toll set from the integrator you have to find your own way.

If your frontend is based on Spice/Verilog/VHDL/VHDL-AMS

and the backend verification rule set is in Calibre

I suggest

SchematicEntry: ECS Cohesion(Sillicon Canvas)
MixedSignalSimulation: Smash Dolphin
DigitalSimulation: ModelSim Mentor
LayoutEntry: Laker Silicon Canvas

Calibre is a little bit expensive but seems the only way to make extractions to spice and are supported by foundries. The backannotation flow is the most critical fro choosing the right tool set. If you consider mixed signal backannotation. That means SDF for gates and RC for analog nets there is no working tool at all.
 

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