microstrip layout, print tolerances

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hi
when we design a rf layout for example in ADS, and then send it to a PCB Manufacturer,
they print the layout on a laminate.
in the photo-etching process, several undesirable effect will occur on pcb trace width.
can anyone explain what type of effects can occur. and how we can compensate for that errors (pcb fabrication errors)?
is offseting the boundry of trace, an issue?

thanks.
 

Nothing you can compensate for. Expect the copper structures to be reproduced typically with designed size, but variations of +/- 50 µm trace width can occur in usual high density process (100 µm minimal width/spacing), more in lower quality process.

Also considerably variations in substrate height and permittivity must be considered, refer to substrate manufacturer specifications.

If these variations can't be accepted, order impedance controlled manufacturing. Contact your PCB manufacturer for details.
 
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thanks sir FvM,

in ADS CookBook (v2):

in part b, it seems to said that we may offset thickness/2 the trace width for compensating the error.
 

I have seen a PPT presentation where Monte-Carlo simulation was used to evaluate tolerances impact on the design and choose better values for capacitors and resistors. I think it was ADS, but i googled for it and did not found it. Maybe the same method could be applied to microstrip element width/spacing.
 
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thanks dear Terminator3.
i did testing my first edition of pcb that the length of p-p was about as large as 20 lambda.
for such a complicated circuit it was hard to predict the effects of fab errors.
but now, i know the errors due to test results.
i wish to find some tips for compensating the fab-errors. although dear FvM said that no need to compensation.
another error may be curving inner corner of 90deg bends in the etching process.

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i am using rogers duroid laminate, I thought rogers have the best reliable laminates... i must recheck datasheet.
 

i did testing my first edition of pcb that the length of p-p was about as large as 20 lambda.
for such a complicated circuit it was hard to predict the effects of fab errors.
but now, i know the errors due to test results.
Click to expand...
If you have already a prototype, what are the actually observed dimension errors?

Problem is however, that a new batch must not necessarily achieve exactly the same size variation as the prototype, unless the manufacturer can assure you to keep everything constant. Most likely he can't. That's particularly the case for prototype production in pool service.

That's why impedance control is the preferred method to reproduce RF/high speed PCB exactly.

Some typical parameters of the PCB manufacturing process can be of course reflected in your design simulation like the trapezoidal trace shape and the said corner rounding.
 

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It's a question how much the Transmission Line (or any line ) is critical ?? For instance a TL that is used simply match an impedance at 500 MHz is much less critical compare to another one that works for a VCO @ 60GHz..
So it depends on the specific application.
 

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