micron ddr sysverilog model | Read rand addr | how to get 0s ( not Xs ) ?

[ranke]

Hi,
We run micron ddr4 systemverilog model, it returns 'X' when read from a new address, it returns 'X' while we sould prefer to get '0'.


Thanks,
Ran.

 

[KlausST]

Hi,

most probably the contents of the RAM are not defined after pwer up.
--> if you want to read "0" you first have to write "0".


Klaus

 

[dpaul]

You must verify certain things with the RAM model first.
There should be a signal called calibration_complete. Please check if that is asserted HIGH at some point as simulation proceeds. Only after that you can W/R from the RAM. Next you need to make sure 0s exist at the address from which you prefer to read.