All protection follows Ohm’s Law. You decide on the current and voltage limits then look up the clamp voltage with your current limiting R and see if it is less than the Absolute Max. Raising the input R is the best way to reduce the rise and at some point in your career you will learn how to estimate the Rs bulk resistance of these devices with the Vth threshold to match the max. Specs. Rd~<k/Pmax rating. k=0.5 +/- 50% is what I use for diodes.
Logic device protection can be very different from analog. But if the limits are the same, in CMOS even the implementations can be different. 50 years ago high voltage CD4000 CMOS used two stages of 50k with a 5mA Schottky diode for low capacitance. Now with 5.5V and 3.6V logic etc, the speed demands even lower input capacitances, so each OEM developed more complex arrangements.
Adding low C clamp protection preserves speed found in TVS devices and terminate long wires with an active terminator. If you don’t need the BW adding a large C with matched cable impedance in series before it, then you must prevent power cycling fast or with current limiting R after C. This initial condition must l prevent over current on the internal protection diodes or FETs. The input current limiting is very small to reduce C input and make it faster than the substrate SCR latch-up PNPN to protect it.
In short neither presented have design specs which you need to judge if a design is better or not. So define by some estimate of your signal BW, interference expected ( e.g. nearby arc welders, AC line transients) or just follow industry best practices using TVS , filters etc. for your environment.