Microcontroller input protection

[Saeedk9574]

Hi everyone,
I have some questions about MCU input protection although this issue has been asked many times in this forum on other ones, I got baffled by different answers. Thank you in advance for your insights!

In my project, I will use both digital input (for motion detector) and ADC input (for temperature and photocell sensors). First of all, I would like to know if digital input and ADC input protection circuits are different or not?

Second, in this regard, which of these circuits is recommended, or is there any other circuit that you suggest to use for digital and ADC input?

 

[andre_luis]

If your design does not have any restrictions with conditional configuration before integration, I would consider adding an optocoupler in series, not by-passing it through a strap when using with sensors that are not self-biased.

 

[barry]

Adding capacitance on any input may add some protection, but will slow things down and perhaps negatively affect performance; you need to take that into account. And a 20 MEGOHM input resistor seems WAAAAAAAY too large.

 

[danadakk]

Adding capacitance on any input may add some protection, but will slow things down and perhaps negatively affect performance; you need to take that into account. And a 20 MEGOHM input resistor seems WAAAAAAAY too large.

20 Megohm x input leakage current = disaster as Barry says. You may not
be able to achieve any noise margin for logic levels at input. Not unusual
to have 1 uA leakage, I will let you calculate what that means with a LOGIC
input level applied to a 20 MegOhm R at the actual input to a CMOS gate.


Regards, Dana.

 

[Saeedk9574]

If your design does not have any restrictions with conditional configuration before integration, I would consider adding an optocoupler in series, not by-passing it through a strap when using with sensors that are not self-biased.

Thanks for your reply.
Unfortunately, I can not use optocoupler because GND is connected in all circuit. So the only option is diodes. But I do not know which circuit is appropriate to use for ADC and digital input.

--- Updated Oct 20, 2024 ---

20 Megohm x input leakage current = disaster as Barry says. You may not
be able to achieve any noise margin for logic levels at input. Not unusual
to have 1 uA leakage, I will let you calculate what that means with a LOGIC
input level applied to a 20 MegOhm R at the actual input to a CMOS gate.


Regards, Dana.

This 20Mohm is the inside MCU protection circuit. Maybe it differs from one MCU to another. On the whole we dont choose it.

 

[danadakk]

This might help(some general concepts and considerations) -

https://annas-archive.org/slow_download/717707c8994739762118aa7362625bc0/0/0

Regards, Dana.

 

[andre_luis]

Unfortunately, I can not use optocoupler because GND is connected in all circuit. So the only option is diodes.

There is no impediment on using an optocoupler in circuits where GND is common to both input and output.

Your original question was concerned on "Microcontroller input protection", and in this sense, indeed, in your case, the optocoupler would not offer any protection against common mode EMI, but it would improve somehow against differential mode ones.

 

[D.A.(Tony)Stewart]

All protection follows Ohm’s Law. You decide on the current and voltage limits then look up the clamp voltage with your current limiting R and see if it is less than the Absolute Max. Raising the input R is the best way to reduce the rise and at some point in your career you will learn how to estimate the Rs bulk resistance of these devices with the Vth threshold to match the max. Specs. Rd~<k/Pmax rating. k=0.5 +/- 50% is what I use for diodes.

Logic device protection can be very different from analog. But if the limits are the same, in CMOS even the implementations can be different. 50 years ago high voltage CD4000 CMOS used two stages of 50k with a 5mA Schottky diode for low capacitance. Now with 5.5V and 3.6V logic etc, the speed demands even lower input capacitances, so each OEM developed more complex arrangements.

Adding low C clamp protection preserves speed found in TVS devices and terminate long wires with an active terminator. If you don’t need the BW adding a large C with matched cable impedance in series before it, then you must prevent power cycling fast or with current limiting R after C. This initial condition must l prevent over current on the internal protection diodes or FETs. The input current limiting is very small to reduce C input and make it faster than the substrate SCR latch-up PNPN to protect it.

In short neither presented have design specs which you need to judge if a design is better or not. So define by some estimate of your signal BW, interference expected ( e.g. nearby arc welders, AC line transients) or just follow industry best practices using TVS , filters etc. for your environment.

 

[Saeedk9574]

All protection follows Ohm’s Law. You decide on the current and voltage limits then look up the clamp voltage with your current limiting R and see if it is less than the Absolute Max. Raising the input R is the best way to reduce the rise and at some point in your career you will learn how to estimate the Rs bulk resistance of these devices with the Vth threshold to match the max. Specs. Rd~<k/Pmax rating. k=0.5 +/- 50% is what I use for diodes.

Logic device protection can be very different from analog. But if the limits are the same, in CMOS even the implementations can be different. 50 years ago high voltage CD4000 CMOS used two stages of 50k with a 5mA Schottky diode for low capacitance. Now with 5.5V and 3.6V logic etc, the speed demands even lower input capacitances, so each OEM developed more complex arrangements.

Adding low C clamp protection preserves speed found in TVS devices and terminate long wires with an active terminator. If you don’t need the BW adding a large C with matched cable impedance in series before it, then you must prevent power cycling fast or with current limiting R after C. This initial condition must l prevent over current on the internal protection diodes or FETs. The input current limiting is very small to reduce C input and make it faster than the substrate SCR latch-up PNPN to protect it.

In short neither presented have design specs which you need to judge if a design is better or not. So define by some estimate of your signal BW, interference expected ( e.g. nearby arc welders, AC line transients) or just follow industry best practices using TVS , filters etc. for your environment.

Thank you, doing some research, I found out TVS is recommended especially for ADC. Can you recommend some TVS part numbers that are common.

 

[D.A.(Tony)Stewart]

Thank you, doing some research, I found out TVS is recommended especially for ADC. Can you recommend some TVS part numbers that are common.

no but DigiKey's stock sorted will tell anyone what's common or sorted by price.

 

[danadakk]

Considerations :

https://www.diodes.com/assets/App-Note-Files/TVS-in-Automotive-Applications.pdf

https://fscdn.rohm.com/en/products/databook/applinote/discrete/diodes/selection_method_and_usage_of_tvs_diodes_an-e.pdf

https://www.ti.com/lit/pdf/slvae37

Leakage current can be a factor depending on how ADC input is conditioned in
the overall signal path into ADC.


Regards, Dana.