Methods to reduce IR drop

[medasunil]

irdrop

Hi All,

Below are the methods i know to reduce IR drop
1. Adding more stripes
2. Spread the logic (if hotspots are at congested areas)
3. Using low power cells
4. Adding proper vias
5. Clock gating
6. Proper CTS structure (Minimising clock buffers in clock tree as they switch very frequently)
please kindly let me know is there are any more methods

 

[raju3295]

decap cell insertion, but it increase leakage power.
and can u explain me,, wht are lowpower cells. and how clock gating decrease IR drop. and how proper CTS srtructre will reduce IR drop specifically,, it reduces dynmaic power.

 

[ivlsi]

What is decap cells? How do they decrease IR-Drop?

 

[rca]

Decap is capacitance cell between the two power rings.
To reduce the IR drop, you could connect the metal filling to a power, for example odd layer to gnd and even layers to vdd.

 

[ivlsi]

Thank you!

---------- Post added at 16:54 ---------- Previous post was at 16:50 ----------

Thank you! As for the delay cells, are they just a chain on inverters? How do they implemented?

---------- Post added at 16:55 ---------- Previous post was at 16:54 ----------

As for the delay cells, are they just a chain on inverters? How do they implemented?

 

[oratie]

Thank you! As for the delay cells, are they just a chain on inverters? How do they implemented?

Usually, it is a chain of four inverters, where the two middle inverters have non-minimum gate length of transistors.

 

[ivlsi]

two middle inverters have non-minimum gate length of transistors

What does it mean? Why is it done? How do this effect on the delay? Does it increase it? Is it was not enough to put just a chain of regular inverters? Why?

Thank you!

 

[oratie]

What does it mean? Why is it done? How do this effect on the delay? Does it increase it? - Yes, it increase the delay (if you need a big delay, it is prefferably to increase gate length rather increase inverters number in the chain (the cell area will be smaller))

Is it was not enough to put just a chain of regular inverters? Why? - For the small delay cell it is enough to use ordinary transistors. But, in case of big delay, usually, they use big gate length.

 

[ivlsi]

Thank you! Clear enough

 

[yadavvlsi]

Check these links:
https://www.edaboard.com/threads/217088/#2
https://www.edaboard.com/threads/171247/#5
https://www.edaboard.com/threads/234001/#3

 

[jeet_asic]

Decap is capacitance cell between the two power rings.
To reduce the IR drop, you could connect the metal filling to a power, for example odd layer to gnd and even layers to vdd.

how does this reduce IR drops?

 

[rca]

The ir drop is due to not too high resistivity, if you used the metal filling to interconnect the power supply you will reduce the resistivity.

 

[oratie]

how does this reduce IR drops?

If you connect your metal filling to VDD/VSS mesh (usually, metal filling is float), it will add additional capacitance to power mesh. So, it will reduce the IR drop (to get IR drop you need to discharge the capacitance of the power mesh). It does not matter, which layer to connect to vdd or gnd. The problem here is that you may meet some problems with routing (connecting metal filling to power straps) - not enough area to route.

 

[owen_li]

it will add additional capacitance to power mesh. So, it will reduce the IR drop (to get IR drop you need to discharge the capacitance of the power mesh).

Hi.
can you explain it more detailed ?
why adding capacitance will reduce IR drop ?
Thanks!

 

[oratie]

This additional cap (of power network) acts as local charge storage and is helpful in mitigating the voltage drop. When the cells of your design is switching, they consume the power and additional caps will give them their charge (until power supply network will be able to compensate the required power).

I can not explain in more easy way. The bigger capacitance (cap of power straps), the more difficult to discharge it (if you have the same number of your logic cells, it will be more difficult for them to discharge the bigger capacitance of power straps).

 

[owen_li]

This additional cap (of power network) acts as local charge storage and is helpful in mitigating the voltage drop. When the cells of your design is switching, they consume the power and additional caps will give them their charge (until power supply network will be able to compensate the required power).

I can not explain in more easy way. The bigger capacitance (cap of power straps), the more difficult to discharge it (if you have the same number of your logic cells, it will be more difficult for them to discharge the bigger capacitance of power straps).

Thanks very much for your quick response, oratie.
I have ever heard that Decap cell can be used as charge pool when the nearby switching instances need charge.
But I haven't seen any document on this use of additional power segment.
Can you provide me some document or link on this topic?
In my opinion, I think It is because of the Resistence reduction on power and ground routing that be helpful to mitigatint IR drop.
when connecting the metal filler with power and ground, the resistence of power and ground routing will be reduced coz of parallel connection.
So result of I*R comes down, then the IR drop comes down.

Do you think so ?

 

[anantha.bhat]

Many Physical design techniques are being discussed in this thread. But if you split I and R parts in IR analysis, avoiding huge rush of current due to simultaneously switching outputs (SSO) is a design approach. Reduce i(t). v(t) profile also changes. I believe, Apart from steady IR drop, ( if any) it is this sudden rush of current and its effect has earned it a name charge starvation.

IR is one of the factors in RV (Reliability Verification) along with EM, (ElectroMigration). Do remember that these two should be solved together. If you divert lots of current elsewhere to ease IR drop, other polygons can cross either avg, absolute avg, or peak EM limits.

 

[owen_li]

Thanks very much for your quick response, oratie.
I have ever heard that Decap cell can be used as charge pool when the nearby switching instances need charge.
But I haven't seen any document on this use of additional power segment.
Can you provide me some document or link on this topic?
In my opinion, I think It is because of the Resistence reduction on power and ground routing that be helpful to mitigatint IR drop.
when connecting the metal filler with power and ground, the resistence of power and ground routing will be reduced coz of parallel connection.
So result of I*R comes down, then the IR drop comes down.

Do you think so ?

Hi oratie.

Can you help put some your comments?

Thanks!

 

[oratie]

In my opinion, I think It is because of the Resistence reduction on power and ground routing that be helpful to mitigatint IR drop.

Yes, the resistance reduction of power mesh will help in IR-drop reduction.

when connecting the metal filler with power and ground, the resistence of power and ground routing will be reduced coz of parallel connection.

Here is misunderstanding. There is a metal fill - it is just a pieces of metal (which can be inserted by the tool). If you connect one edge of this metal to the power/ground, it will not reduce the resistance, because the other edge still is unconnected. It will just add an additional capacitance to the power mesh. Yes, if you have enough empty area, you may place this metal fill polygon parallel to the power strap and connect both edges to the strap - in this case, the resistance will be smaller. Good to IR-drop reducing.

The metal filler cell - it's a std. cell, with metal pieces and transistors (usually), these cells are named as DCAP cells. They adds additional capacitance to the power mesh and reduce the IR-drop. The problem here is that such cells have some leakage power. So, if you add them a lot, the leakage of your chip will be big. These cells must be inserted only in that areas, where the IR-drop is big.