Methodologies for RFIC design?

Hi all I've never tested a RFIC-design package. I wonder which the methods are for designing.

Does one usally design with emphasis of minimizing mismatches like in conventional microwave design, with S-parameters, gain-circles etc ?

Or is it the case that since the wavelengt is much bigger than the chip dimensions (if its not say, 200 GHz) that one approach the problem as in conventional low frequency IC-design ?

Kindest regards,
StoppTidigare

P.S. I need a book/article that thoroughly expalains definitions of and how to calculate sensitivity, selectivity, CR, Spurs,IP2,IP3,IPN,1/2 IF rejection,Take over gain, IM. I am reading Peter Vizmuller , "RF-design guide", but I find it too compact. Not easy to understand.

Hi again all.

Hey, help me out here...

Why did AWR launch Analog Office, when they had Microwave Office ?

Why is there a difference designing a 5 GHZ amp on duroid or FR4 compared to doing it in a chip.

As far as I understand the design methodologies are the same as LF IC design, but theres a bigger emphasis on EMC on the layout part.

Regards,
StoppTidigare

Hi StoppTidigare

please clarify: "Hi all I've never tested a RFIC-design package. I wonder which the methods are for designing." -> are you interesed in design or in measurement of RF IC?

"Does one usally design with emphasis of minimizing mismatches like in conventional microwave design, with S-parameters, gain-circles etc ?": Usually in lumped circuit world (inside ICs) criteria are similar (not always!!) to analog circuit design; in distributed circuit worls (outside ICs) criteria are: Spar, power match and so on.

"Or is it the case that since the wavelengt is much bigger than the chip dimensions (if its not say, 200 GHz) that one approach the problem as in conventional low frequency IC-design ? ":
inside ICs lumped component models are widely used. Their derivation is often from Spar measurement (MW probes and deembedding).

"Why did AWR launch Analog Office, when they had Microwave Office ? " Maybe commercial reasons...competition with Cadence and Agilent is hard...

"Why is there a difference designing a 5 GHZ amp on duroid or FR4 compared to doing it in a chip.": using ICs you may have first of all the benefit of integration, that means space, cost etc. You have almost for free the possibility to use complex structures with lot of transistors.

"As far as I understand the design methodologies are the same as LF IC design, but theres a bigger emphasis on EMC on the layout part." Right but not only; for example: designing a receiver in a 12mm2 (PLL, LNA, Mixer, IF AGC) you need very good strategies to isolate blocks!!

bye
Mazz

Mazz,

Thank you for the important tips

Regards
T Zul