metal width of a bus

[melkord]

Hello,

I have some doubts about the layout of a long wire or bus.
Q1. For a given bus width, should I prioritize the spacing between wires or wire's width? Obviously, I wish I can have as less cross talk and time constant as possible.
Q2. For a given bus length, it seems that I cannot reduce the time constant because the R and C behave in the opposite direction w.r.t. the width. Am I missing something here?

Apologize if these turn out to be very basic questions.

 

[jjx]

Wtot = N*W + (N-1)*d

Assuming sidewall cap is dominating.

R ~ r0 / W and C ~ c0 / d

Targeting min t = RC ~ min r0c0 / dW ~ t0 / dW

where distance between wires is

d = (Wtot - NW) / (N-1) ~ w - W

And time constant thus

t ~ 1 / (w-W)*W ~ 1/W + 1/(w-W)

Taking derivative to find extreme value

dt/dW = -1/W^2 + 1/(w-W)^2 = 0 => (w-W)^2 - W^2 = 0 => -2wW + w^2 = 0 => W = w/2

Yields approximately

W ~ Wtot/2N

i.e. as wide as spacious.

Does it make sense, I do not know...

 

[dick_freebird]

Delay will probably be a wash (w/ width) on wide busses because plate
capacitance goes up while resistance goes down. But this has some
nuances when you get to thinner traces closely spaced because fringing
C can match or exceed plate C. Whether you'd see this in post-layout
parasitics depends on how diligent the PDK developers were, in how they
figure trace capacitances. Separation reduces line-line but not line-substrate C.
A layer higher in the stack will have trivial plate and dominant fringing
capacitances, and respond most to spacing.