Metal Oxide Semiconductor in strong Inversion

[Robotduck]

MOS (p type)
1) General Question: Why thin charge sheet on the metal side ? Is it because positive bias on metal side will attract the electrons leaving immobile positive ions at the metal -oxide interface ? If yes then why not we get this thin charge sheet at surface of the metal where we have the positive bias ?
2) Figure a) and b) are the cases of strong inversion. Figure b)-For high frequency signals, electrons at the semiconductor oxide interface do not get enough time to change ( I follow that ), but how come the charge in the bulk close to the depletion region changes with these high frequency signals and causes the change in the depletion region in the bulk ( which is bothering me )?
3)In Figure c) if we change the voltage ( ranging from accumulation to strong inversion )quickly, then the system does not have enough time for strong inversion but again - how come the charge in the bulk is responding with this change ?
4) How come the charge in the Metal is responding to these changes in figure b) and c) ? This also has the electrons as a majority carriers ?

Thank you in advance for taking time to answer these questions !!

 

[Robotduck]

Query 1 is solved. I follow that.

For 2), 3), 4), the concept that I don't understand is that how come the electrons at the interface can not respond to the high frequency signals instead the holes in the bulk can which causes the change in the depletion region in the bulk ?

 

[dick_freebird]

I believe you're looking at charge pumping C-V for the
purpose of quantifying the trap density.

The "frequency" high or low pertains to the trap lifetime
(reciprocal). There are all kinds of traps. Shallow ones
near the interface can populate or depopulate quickly.
Ones further into the oxide will "toggle" slower and with
more field dependence. Ones with a more favorable
electron or hole affinity will be slower / unlikelier to
let go. If the trap is in its natural state (populated or
not populated) at equilibrium and you push a carrier
into it, you changed it. So there will be short-term
hysteretic behavior (if you go back a step, it is not
the same as it was, you have to overtravel or wait
to return to equilibrium). "Slow" is the compromise from
"DC" because at DC nothing ever gets done. "Fast"
(and varyingly so) will show you the time domain
evolution / devolution of charge trapping and from
this device engineers can tell you stuff about where
the traps are and what type and maybe how you'd
get rid of some.

Depletion region / bulk behavior has not to do with
traps, it's all free carriers (or absence) at drift velocity.
Not some gaggle of lost carriers in an oxide-interface
thicket, stumbling about.

Metal (or highly doped conductive silicon) is the same,
carriers are there and free to move with any field at all.

 

[Robotduck]

I believe you're looking at charge pumping C-V for the
purpose of quantifying the trap density.

The "frequency" high or low pertains to the trap lifetime
(reciprocal). There are all kinds of traps. Shallow ones
near the interface can populate or depopulate quickly.
Ones further into the oxide will "toggle" slower and with
more field dependence. --------( I do not think this is true. for high frequency the charge carriers at the interface do not have much time to change, its the charge at the bulk . IN addition to this : I am sure there are traps in the semiconductor material but the electrons charge carriers at the interface are because of the positive bias at the metal. There is a band bending at the interface ( Fermi level will be closer to the Ec) and I believe the electrons fill the empty states in the conduction band because of the high positive bias at the metal )

-Ones with a more favorable
electron or hole affinity will be slower / unlikelier to
let go. If the trap is in its natural state (populated or
not populated) at equilibrium and you push a carrier
into it, you changed it. So there will be short-term
hysteretic behavior (if you go back a step, it is not
the same as it was, you have to overtravel or wait
to return to equilibrium). "Slow" is the compromise from
"DC" because at DC nothing ever gets done. "Fast"
(and varyingly so) will show you the time domain
evolution / devolution of charge trapping and from
this device engineers can tell you stuff about where
the traps are and what type and maybe how you'd
get rid of some.

Depletion region / bulk behavior has not to do with
traps, it's all free carriers (or absence) at drift velocity.
Not some gaggle of lost carriers in an oxide-interface
thicket, stumbling about.
----- I am sorry but I do not follow this.


Metal (or highly doped conductive silicon) is the same,
carriers are there and free to move with any field at all.

Please correct me if I am wrong. I also attached a figure with the first message. I have a hard time in understanding - why would the carrier at the interface won't have enough time to change with the high frequency signal but the carriers in the bulk will ?

 

[Robotduck]

Is it related to mobility ? I can not figure out why the electrons at the interface can not respond to fast changing signal at the input but carriers in the bulk can which changes the depletion width- please see the figure attached with the first message.

 

[dick_freebird]

When you say "at the interface" it appears you assume that
these are all carriers sitting in bulk silicon, leaning up against
the wall just smoking a cigarette and pretty much free to do as
they please. And probably some subsidiary assumptions like
"the interface" being abrupt, uniform on either side (perfect
silicon below, perfect insulator above) and so on.

But of course this is a grown oxide and "the interface" is
made over some atomic distances, transitioning from pure
silicon (doping aside) to pure well ordered SiO2 (fat chance)
with a brief interval of randomly-chemically-involved silicon-
oxygen stew. It's in this region that many defects / traps
are found. Carriers that are trapped, by definition cannot
move as they'd like. Until they are freed to the bulk silicon
they have nothing like bulk silicon carrier attributes (energy,
mobility).

 

[Robotduck]

I understand partially what you are saying but still unclear about the fast response of carriers in bulk with respect to high frequency? Lets consider an ideal situation then how will you explain this ?

 

[dick_freebird]

Before we go any further, how about you quantify:


"fast" and "slow" sweep time for a C-V measurement
on normal equipment such as shown


minority carrier lifetime in bulk regions


transit time for your device structure, characteristic
switching time or 1/fmax for your device


"Fast" on a Kiethley is still glacial compared to any modern
transistor's performance, but not necessarily "slow" compared
to some of the longer-lived traps (I have seen sub-Hz RTN
on small SOI transistors)





Your C-V structure in the interests of measurement is going
to be so large that it will not show you the individual detraps
but what you see on the "slow" curve is the cascade of them -
like water being squeezed back out of a sponge, you don't
get it all if you don't wait (the "fast" curve).


Meanwhile in the bulk of the explicit device, in normal operation,
Niagara Falls.

 

[timof]

Robotduck -

These are classical C-V curves of MOS structure, having nothing to do with traps or interface defects.
See classical books by S.Sze or E.Nicollian.
This is a standard response of a clean, ideal system (real silicon is very close to this).

The key to understand the behavior at low vs high frequency is the nature of the inversion layer electrons, where they come from, and how fast.
In the absence of a direct contact to the reservoir of electrons from N+ doped regions (such as source/drain regions in MOSFET, contacting the inversion layer), electrons in the inversion layer (minority carriers in p-doped semiconductor) appear from thermal generation process. This process is quite slow in high-purity silicon, used to make wafers and chips.
The generation time can be of the order of seconds or more at room temperature - it is strongly temperature dependent, and is decreasing with increased temperature.
So, inversion layer electrons do not appear and disappear instantaneously, it takes final time for them (for their concentration) to respond to changing voltage.
This - their response time, or life time - is what distinguishes the regime of low frequency response vs high-frequency.
When frequency of (small-signal) AC signal applied to the gate is low - lower than the inverse response or life time, inversion layer charge has time to respond, and so you get the curve (a) in your plots.
Your plots are absolutely correct.
When frequency is high, inversion layer charge stays constant, and changes of the charge density in the silicon happens at the edge of the depletion region.
That charge - majority carriers in the semiconductor, holes in p-doped silicon - responds very fast.
Its response time is equal to dielectric relaxation time in semiconductor (dielectric relaxation time - tau=rho*eps - tells how fast non-equilibrium charge dissipates under the action of electric field forces generated by this charge itself).
It is in the picosecond range for semiconductor doped to a reasonable level (1e17 cm-3).
So, it is very fast, much faster than any (inverse) frequency used for capacitance measurements.

Now, when you sweep the voltage fast, from negative to positive, there is no time to form the inversion layer of electrons, and depletion layer becomes much wider than in the steady state case.
This case is called deep depletion.
The capacitance goes below its high-frequency steady state value.
If you wait long enough, after sweeping from negative to positive voltage, the inversion layer is formed, and capacitance goes to its steady state value (low frequency or high frequency value, depending on the frequency).

This is a basic semiconductor physics and semiconductor device physics level explanation.

Max