If the object is a low-level cell for a library, then
cell design rules might include a requirement
(or emphatic suggestion at least) to not throw
routing barriers, constraining the layout to lower
metal layers. Perhaps less of a thing today, but
back when you had only 2-3 layers of metal it
was common to insist that standard logic cells
used only metal1; in 6LM technology I saw this
relax to allow metal2 as well.
Kind of surprising that a MIM cap dielectric
would show a strong tempco. Is it perhaps not
a SiO2, but something more polar (like Si3N4)?
The Er (relative permittivity) of 7.5 is neither
SiO2 nor Si3N4. It is close to alumina, indicating
the dielectric may be formed by oxidation of
the bottom plate (in which case you care a lot
about how that etch process before the MIM
oxidation, leaves the surface condition).
A paper on Al2O3 dielectrics indicates a pretty
low TC at sensible IC application temperatures
(albeit it's about polycrystalline Al2O3, which
may deviate from single-crystal alumina, and
who's to say which the MIM dielectric most
resembles)?
Anybody know how to strip Google search
embedded link garbage back to a direct URL?