Mesuring Discharge time

Hi members,
I need to measure the discharge time of a Latch. I used spectre to simulate the Latch. Simulation was done with the extracted parasitic parameters R and C in the latch. PLS consisted that the latch holds a 1 Logic (1Volt) and once this is done the input of the Latch and the clock signal are maintainted to 0 Logic (0 Volt). I set the simulation time to 10ms but it seems that the latch'output doesn't change. Even by extending the simulation time to 1 second the output of the latch remain the same at 1 Volt like if there is no leakage at all.
Do you have any Idea what causes that and why the Latch does not discharge.

Assuming the latch continues to be powered, it would take a very long time for a latched 1 to become a 0. Like days, if ever. Why do you expect a powered latch to discharge in 1s?

randyest said:

Assuming the latch continues to be powered, it would take a very long time for a latched 1 to become a 0. Like days, if ever. Why do you expect a powered latch to discharge in 1s?

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I know that this is different but, since DRAM require te be refreshed each 64 ms I though that 1 s is a lot for my latch (please see second figure of the following post.

Sorry, I'm not familiar with that kind of "latch" in figure 2. Figure 1 looks like latches I know, and the feedback loop makes it hold a 1 essentially forever. DRAM is very different -- usually just a MIM capacitor or trench capacitor, which of course will discharge quickly and requires refresh.

randyest said:

Sorry, I'm not familiar with that kind of "latch" in figure 2. Figure 1 looks like latches I know, and the feedback loop makes it hold a 1 essentially forever. DRAM is very different -- usually just a MIM capacitor or trench capacitor, which of course will discharge quickly and requires refresh.

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The style of circuitry shown in figure 2 used to be very common, particularly in NMOS devices (when running from 5 volts, a single NMOS transistor will do an adequate job of transferring a high level to the next gate). The popular 6502 microprocessor used that sort of thing a lot in its design, as did the display ASIC for the the Atari 2600 Video Computer System and display "memories" (shift registers) used in Steve Wozniaks' Apple I and Breakout game.

The latch in the first figure will never have any continuously floating nodes, but it may have a momentary partial vdd-ground short when the clock input changes (e.g. if D is low and Q is high, and the clock rises, the bottom-left NMOS transistor will turn on, trying to pull S low, while the top-right NMOS transistor is still on (trying somewhat less strongly to pull S high). At the expense of more chip real-estate, one could tweak the clocks going to the four transistors to leave a small gap rather than a period of overlap. I don't know how long a gap could be tolerated in modern CMOS, but I'm pretty sure a few nanoseconds shouldn't hurt.

FYI, I believe the 6502 had a minimum clock speed of 100MHz, which would suggest that in 1970's-era silicon, a node would hold its value for at least 10us. Of course, today's silicon uses smaller features but is also probably less "leaky".

I wouldn't rely upon simulation to be at all accurate when it comes to such leakage, unless it declares that any node becomes "unknown" if it is undriven for too long, and the time in question is set well short of the worst-case limits for the silicon process one is using.

Very well explained !
Thanks you so much supercat !
So the latch will not lose it's information soon and simulation time has to be extended. Unfortunately such a simulation will take days of running I suppose and simulation file will be huge.

supercat said:

I wouldn't rely upon simulation to be at all accurate when it comes to such leakage, unless it declares that any node becomes "unknown" if it is undriven for too long, and the time in question is set well short of the worst-case limits for the silicon process one is using.

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I consulted the documentation on the process in the hope of finding a constant K letting calculte the Leakage current according to the Transistor's dimentions. Unfortunately I found nothing except an information saying that the leakage is 80 ma for 1 Kilogate.
I really dont know what it is meant by gate (AND, inverter, etc), can I consider K=80/1000 ?

AdvaRes said:

Very well explained !
Thanks you so much supercat !

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My pleasure.

I consulted the documentation on the process in the hope of finding a constant K letting calculte the Leakage current according to the Transistor's dimentions. Unfortunately I found nothing except an information saying that the leakage is 80 ma for 1 Kilogate.
I really dont know what it is meant by gate (AND, inverter, etc), can I consider K=80/1000 ?

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Eighty milliamps, microamps, or nanoamps?

Unless a manufacturer offers up specific numbers about the worst-case self-discharge time of a gate, I wouldn't assume very much. It's probably safe to assume that the time a floating node will hold its value is equal to at least a few gate switching delays (a lot of logic would fail if that weren't the case) but I don't know how far you can push it. Note that manufacturers generally try to minimize gate capacitance. Although they also try to cut leakage, they may or may not decrease it as much as they decrease gate capacitance.

I would not be at all surprised if the manufacturer doesn't offer any specs that would guarantee that any particular floating-gate hold time measured in seconds (as opposed to, e.g., gate delays) would work. I don't think a manufacturer is apt to refrain from any opportunity to minimize gate capacitance merely to allow floating-gate designs to work. Some manufacturers might know that they're not realistically going to reduce gate capacitance below some level in the immediate future, and might document that in their specs, but I wouldn't count on much.

It might be fun and interesting to include a little test circuit in some other design to see how long floating gates can hold data; I wouldn't think it worthwhile to fab a chip just for the purpose of testing that out, though. Note that even if you discovered that a particular process technology seemed to be able to hold data reliably for a millisecond, I wouldn't want to actually rely upon it to hold data for anything beyond a very small fraction (1/1000 or less) of that. I thus wouldn't advise using the measurements from such testing for any significant purpose, but I'd personally be curious to know what they would be with typical modern processes.