architecture Behavioral of scheduler is
signal s_w0 : std_logic_vector (511 downto 0);
signal s_w : std_logic_vector (31 downto 0);
begin
process (load,t,clk)
variable s_iw : std_logic_vector (31 downto 0);
begin
if ((clk = '1') and clk'event) then
if (load = '1') then -- 0 <= t <= 15 first 512 bit block
case t is
when "0000000" =>
s_w <= MessageIn(31 downto 0);
when "0000001" =>
s_w <= MessageIn(63 downto 32);
when "0000010" =>
s_w <= MessageIn(95 downto 64);
when "0000011" =>
s_w <= MessageIn(127 downto 96);
when "0000100" =>
s_w <= MessageIn(159 downto 128);
when "0000101" =>
s_w <= MessageIn(191 downto 160);
when "0000110" =>
s_w <= MessageIn(223 downto 192);
when "0000111" =>
s_w <= MessageIn(255 downto 224);
when "0001000" =>
s_w <= MessageIn(287 downto 256);
when "0001001" =>
s_w <= MessageIn(319 downto 288);
when "0001010" =>
s_w <= MessageIn(351 downto 320);
when "0001011" =>
s_w <= MessageIn(383 downto 352);
when "0001100" =>
s_w <= MessageIn(415 downto 384);
when "0001101" =>
s_w <= MessageIn(447 downto 416);
when "0001110" =>
s_w <= MessageIn(479 downto 448);
when "0001111" =>
s_w <= MessageIn(511 downto 480);
s_w0 <= MessageIn;
when others =>
s_w <= x"00000000";
end case;
else
s_iw := s_w0(95 downto 64) xor s_w0(255 downto 224) xor s_w0(447 downto 416) xor s_w0(511 downto 480);
s_w <= (s_iw( 30 downto 0) & s_iw( 31));
s_w0(511 downto 0) <= (s_w0(479 downto 0) & s_iw(30 downto 0) & s_iw(31));
end if;
end if;
end process;
W <= s_w;
end Behavioral;