Merging multiple VHDL designs

Hi all!

I have a top-level VHDL design composed from a multiple sub-designs.
In order to synthesizes it, I have to add all the sub-files to my workspace (rather it ISE or QUARTUS), and it is very exausting each time...

Is there any method to compact all these designs (entities and architectures) in one file (library or package) and then just instantiate them?

If so, can anyone suggest an example code?

Thanks,

qashq11 said:

Hi all!

I have a top-level VHDL design composed from a multiple sub-designs.
In order to synthesizes it, I have to add all the sub-files to my workspace (rather it ISE or QUARTUS), and it is very exausting each time...

Is there any method to compact all these designs (entities and architectures) in one file (library or package) and then just instantiate them?

If so, can anyone suggest an example code?

Thanks,

Click to expand...

i don't know exactly what you want , but in altera you can pack your entire project into one file call "file.QAR"

Are you creating a new project every time you synthesise the project?

I'm not creating it each time, but to clearify I give the following example:

Let's assume that I want to design a simple UART which composed from 3 modules, and which one of then composed from 2 other modules, and so on...
If I want to compile the UART top-design I have to add all these modules files to my workspace.
OK - of course, in this case this is a quite simple task - but what happens when I design a project with 50 modules... that's become a big problem!

I prefer to use a more generic method rather than a tool-oriented method like QUARTUS.

I think the key is to use a library but I don't know how to...

You can modify the quartus file yourself (its just a text file) so you could probably write some procedure for generating it.
Or add a .qip file to the directory with all the source code in it, add the files in that directory to the qip file, then add the qip file to the qaurtus project.

But at the end of the day, you set up a large project once (you know you can add multiple files in one go right?).

My current project has over 1000 source files. Im sure it was a chore when first set up, but its done now.

Look at system design section (chapter 10 and 11) of the book "Circuit_design_with_VHDL_by_Volnei_A._Pedroni"

For Xilinx, you can generate the project with a script. Each tool is a little different, eg XST-only vs ISE vs planahead vs vivado. Quartus should have some similar features as it does have a TCL interface.

It probably is better to have the quartus project regenerated as it is a text file. If it is placed in a source control tool, conflicts can occur and quartus will try to auto-fix the file...

Libraries allow you to place modules into a different namespace. eg, lib1.my_fifo and lib2.my_fifo. both modules have the same name. work is a special library. It is the default library. For some (or all?) tools, setting "work=lib1" means that work.my_fifo and lib1.my_fifo would be treated as the same within that file. Sadly, VHDL libs aren't always handled the same across tools -- Planahead doesn't allow a single file to be compiled into multiple libraries for example, while modelsim does.