danyxp
Newbie level 6
Does anyone has experience with this tool for asic or fpga synthesis library creation?
I'm tryng to develop a library for old Xilinx XC6200 parts with reconfigurablility capabilities. The only one tool for sinthesis I have is Velab (a free VHDL elaborator for structural HDL designs). Does anyone has a more powerful tool for this purpouse?
Thanks in advance.
I'm tryng to develop a library for old Xilinx XC6200 parts with reconfigurablility capabilities. The only one tool for sinthesis I have is Velab (a free VHDL elaborator for structural HDL designs). Does anyone has a more powerful tool for this purpouse?
Thanks in advance.