czpir
Member level 3
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Hi All
I want to design a memory map decoder for the following scenario.
I am using a 8051 variant with a special memory interface. This has 22 address lines and 8 data lines. This means that potentially 4 mb of memory or i/o can be interfaced.
I want to add 2 mb of SRAM and also 32 bytes of i/o to this microcontroller. This is what I have done
I have connected the address lines A0-A4 to the i/o device and data lines are D0 to D7, I have connected the address lines A0-A21 to the same ones on the SRAM.
This leaves the address line A22 free, I also have an active low CS line which would go low for any i/o or memory access. I also have WR and RD lines.
Any help for on deriving the the CS line for the SRAM and I/O device would be appreciated, can this be done using the 74138 or other ?
CZPIR.
I want to design a memory map decoder for the following scenario.
I am using a 8051 variant with a special memory interface. This has 22 address lines and 8 data lines. This means that potentially 4 mb of memory or i/o can be interfaced.
I want to add 2 mb of SRAM and also 32 bytes of i/o to this microcontroller. This is what I have done
I have connected the address lines A0-A4 to the i/o device and data lines are D0 to D7, I have connected the address lines A0-A21 to the same ones on the SRAM.
This leaves the address line A22 free, I also have an active low CS line which would go low for any i/o or memory access. I also have WR and RD lines.
Any help for on deriving the the CS line for the SRAM and I/O device would be appreciated, can this be done using the 74138 or other ?
CZPIR.