Flow Status Successful - Mon Sep 26 12:17:31 2011
Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition
Revision Name topmodule3
Top-level Entity Name topmodule3
Family Cyclone
Device EP1C20F400I7
Timing Models Final
Total logic elements 410 / 20,060 ( 2 % )
Total pins 80 / 301 ( 27 % )
Total virtual pins 0
Total memory bits 0 / 294,912 ( 0 % )
Total PLLs 0 / 2 ( 0 % )
Total combinational functions 127 / 21,280 ( 1 % )
Dedicated logic registers 98 / 21,280 ( < 1 % )
Revision Name max_mean
Top-level Entity Name max_mean
Family Cyclone IV GX
Total logic elements 143 / 21,280 ( 1 % )
Total registers 98
Total pins 99 / 167 ( 59 % )
Total virtual pins 0
Total memory bits 0 / 774,144 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 80 ( 0 % )
Total GXB Receiver Channel PCS 0 / 4 ( 0 % )
Total GXB Receiver Channel PMA 0 / 4 ( 0 % )
Total GXB Transmitter Channel PCS 0 / 4 ( 0 % )
Total GXB Transmitter Channel PMA 0 / 4 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
Device EP4CGX22CF19C6
Timing Models Final
Total combinational functions 1,655 / 21,280 ( 8 % ) Flow Status Successful - Mon Sep 26 14:12:28 2011
Dedicated logic registers 98 / 21,280 ( < 1 % ) Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition
Revision Name max_mean
Top-level Entity Name max_mean
Family Cyclone IV GX
Total logic elements 1,655 / 21,280 ( 8 % )
Total registers 98
Total pins 99 / 167 ( 59 % )
Total virtual pins 0
Total memory bits 0 / 774,144 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 80 ( 0 % )
Total GXB Receiver Channel PCS 0 / 4 ( 0 % )
Total GXB Receiver Channel PMA 0 / 4 ( 0 % )
Total GXB Transmitter Channel PCS 0 / 4 ( 0 % )
Total GXB Transmitter Channel PMA 0 / 4 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
Device EP4CGX22CF19C6
Timing Models Final
module ram_example
#(parameter FIXED_WIDTH=32, MxN=262144, ADDR_W=log2(MxN))
(
input clk, wr_en,
input [FIXED_WIDTH-1:0] din,
input [ADDR_W-1 :0] wrt_addr,
input [ADDR_W-1 :0] rd_addr,
output reg [FIXED_WIDTH-1:0] dout
);
reg [FIXED_WIDTH-1:0] memX [0:MxN-1];
always @(posedge clk)
begin
if ( wr_en ) memX[wrt_addr] <= din;
dout <= memX[rd_addr];
end
//////////////////////////////////////////////////////////
function integer log2 ( input [31:0] value ); //
begin value = value-1; //
for (log2=0; value>0; log2=log2+1) value = value>>1;//
end //
endfunction //
//////////////////////////////////////////////////////////
endmodule
If my parameter MxN= 262144;
Total combinational functions 127 / 21,280 ( 1 % )
Dedicated logic registers 98 / 21,280 ( < 1 % )
If my parameter MxN= 362144; OR parameter MxN= 162144
Total combinational functions 1,655 / 21,280 ( 8 % )
Dedicated logic registers 98 / 21,280 ( < 1 % )
For the xin_mean<=xin_mean + Xin, it is better to just divide it constantly instead?
Honestly speaking, I don't understand the purpose of the suggestions. If you want to implement a mean value calculation, you should use the correct formula. Or you get a different result. Precalculating blocks of 16 is possible, if the total number is a multiple of 16, but doesn't simplify much in this case. Increasing the accumulator width by 18 bits to account for MxN of 2^18 isn't a big deal for an FPGA.as a first approach - you can add e.g 16 values, divide the result by 16
Honestly speaking, I don't understand the purpose of the suggestions.
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