[SOLVED] MEMORY issue (Compilling with Altera Quaruts)

[chikaofili]

Hello,
I have a stupid question, I successfully compiled my project but I am not sure about the results:

Flow Status Successful - Mon Sep 26 12:17:31 2011
Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition
Revision Name topmodule3
Top-level Entity Name topmodule3
Family Cyclone
Device EP1C20F400I7
Timing Models Final
Total logic elements 410 / 20,060 ( 2 % )
Total pins 80 / 301 ( 27 % )
Total virtual pins 0
Total memory bits 0 / 294,912 ( 0 % )
Total PLLs 0 / 2 ( 0 % )

I dont know why my memory bits is still zero when I have this in my verilog topmodule:

(* ramstyle = "M144K" *) reg [FIXED_WIDTH-1:0] memX [0:MxN-1] ;

memX is a 50x50x 32 bits.

Also, My number of logic gates seems really small. I am implementing something that includes convolution, exponential etc. I would expect the number of logic gates to be more.


Sorry I am new at this.


Thank you

 

[TrickyDicky]

its probably synthesising away a load of logic. Are you sure you dont have a signal stuck at 1 or 0? have you connected the clock properly?

 

[chikaofili]

Thank you for the reply,

I am not sure what you mean by connecting the clock. Sorry I am new to verilog

I am just compiling using Quartus at the moment.

I tried testing just ONE of the modules to see if it is working. It performs mean and max


It works on modulesim

If my parameter MxN= 262144;

Total combinational functions 127 / 21,280 ( 1 % )
Dedicated logic registers 98 / 21,280 ( < 1 % )
Revision Name max_mean
Top-level Entity Name max_mean
Family Cyclone IV GX
Total logic elements 143 / 21,280 ( 1 % )
Total registers 98
Total pins 99 / 167 ( 59 % )
Total virtual pins 0
Total memory bits 0 / 774,144 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 80 ( 0 % )
Total GXB Receiver Channel PCS 0 / 4 ( 0 % )
Total GXB Receiver Channel PMA 0 / 4 ( 0 % )
Total GXB Transmitter Channel PCS 0 / 4 ( 0 % )
Total GXB Transmitter Channel PMA 0 / 4 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
Device EP4CGX22CF19C6
Timing Models Final

If my parameter MxN= 362144; OR parameter MxN= 162144;

Total combinational functions 1,655 / 21,280 ( 8 % ) Flow Status Successful - Mon Sep 26 14:12:28 2011
Dedicated logic registers 98 / 21,280 ( < 1 % ) Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition
Revision Name max_mean
Top-level Entity Name max_mean
Family Cyclone IV GX
Total logic elements 1,655 / 21,280 ( 8 % )
Total registers 98
Total pins 99 / 167 ( 59 % )
Total virtual pins 0
Total memory bits 0 / 774,144 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 80 ( 0 % )
Total GXB Receiver Channel PCS 0 / 4 ( 0 % )
Total GXB Receiver Channel PMA 0 / 4 ( 0 % )
Total GXB Transmitter Channel PCS 0 / 4 ( 0 % )
Total GXB Transmitter Channel PMA 0 / 4 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
Device EP4CGX22CF19C6
Timing Models Final

I dont know what is going on?

MxN is just the size of the area.

 

[TrickyDicky]

have you got something connected to the memory so its actually working? if its not directly used the synthesisor will get rid of it.

have you checked out the altera coding guidelines for RAMs in the quartus handbook?

 

[chikaofili]

I tired using reg [0:7] my_ram[0:63] /* synthesis ramstyle = "M512" */;

still no change

 

[TrickyDicky]

that is not how it works.
What you are trying to do is get Quartus to infer a RAM from its behaviour. A simple array lacks the read, write addresses, input and output data connections and a clock that are required to infer a RAM from the code. I seriously suggest you have a read of the quartus handbook in the coding guidlines section https://www.altera.com/literature/hb/qts/qts_qii5v1_02.pdf chapter 10.

 

[chikaofili]

Ok thank you so much, I will read that now.

But without initialing the ram, I still have a problem with the compilation.

If you noticed, it only runs properly for different sizes. I am not sure why.

I just used only registers in the code (see p. message)

 

[FvM]

As a starting point, review the VHDL RAM design templates in the Quartus editor.

 

[chikaofili]

Thank you,
I am looking at that now...


But the main problem is not with the ram.

It is about my 1st reply. I dont understand why the code fails for different sizes.

If it is 512x512 it fails.. But anything but any random bigger and smaller size works

Is there something else i should add to quartus to synthesize a project?

 

[j_andr]

module ram_example 
  #(parameter FIXED_WIDTH=32, MxN=262144, ADDR_W=log2(MxN))
 (
   input    clk, wr_en,
   input      [FIXED_WIDTH-1:0] din,
   input      [ADDR_W-1     :0] wrt_addr,
   input      [ADDR_W-1     :0] rd_addr,
   output reg [FIXED_WIDTH-1:0] dout
 ); 
reg [FIXED_WIDTH-1:0] memX [0:MxN-1];
  always @(posedge clk)
     begin
       if ( wr_en )  memX[wrt_addr] <= din;
       dout <= memX[rd_addr];
     end
//////////////////////////////////////////////////////////
 function integer log2 ( input [31:0] value );          //
  begin  value = value-1;                               //
    for (log2=0; value>0; log2=log2+1) value = value>>1;//
  end                                                   //
 endfunction                                            //
//////////////////////////////////////////////////////////  
endmodule

compare the example with your declarations and usage;
the code syntethized as expected [fitter failed as the
device is too small]

+---------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------+
; Revision Name ; ram_example ;
; Top-level Entity Name ; ram_example ;
; Family ; Cyclone ;
; Device ; EP1C20F400C6 ;
; Total logic elements ; 1,736 ;
; Total pins ; 102 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 8,388,608 ;
; Total PLLs ; 0 ;
+-----------------------------+---------------+

if you can't find the reason why quartus does not
instanciate the memory put here your code, at least
top level I/Os, the mem. declaration and instantiation;
---

 

[chikaofili]

---------- Post added at 17:19 ---------- Previous post was at 17:18 ----------

[/COLOR]Thats the code.

It is used to find the mean of an array and the maximum number.

Xin is the input.

---------- Post added at 17:20 ---------- Previous post was at 17:19 ----------

Thank you!

But for some reason, if I change this parameter MxN= 262144;. I get weird results

 

[j_andr]

If my parameter MxN= 262144;

Total combinational functions 127 / 21,280 ( 1 % )
Dedicated logic registers 98 / 21,280 ( < 1 % )

If my parameter MxN= 362144; OR parameter MxN= 162144

Total combinational functions 1,655 / 21,280 ( 8 % )
Dedicated logic registers 98 / 21,280 ( < 1 % )

262144(dec) is 40000(hex)
362144(dec) is 586...(hex)


in your code you have a division xin_mean<=xin_mean/MxN +Xin/MxN;
in the first case division is just moving (or cutting ) bits,
the second case requires implementing 'real' dividing logic so quartus did;
---

you add thousands of times 32 bit values xin_mean<=xin_mean + Xin
imagine how large the register has to be to hold such adding result without
overflow

 

[chikaofili]

Thank you so much!!!!

Makes sense now... So essentially, because the other one was a multple of two, that was why it was easy.



Thanks again!!

For the xin_mean<=xin_mean + Xin, it is better to just divide it constantly instead? because my array size will always be a (multple of 2)

 

[j_andr]

For the xin_mean<=xin_mean + Xin, it is better to just divide it constantly instead?

as a first approach - you can add e.g 16 values, divide the result by 16, store, the same for next 16 set
and so on, then perform the same on stored values until you have a final number;
some memory and a clever FSM have to be engaged;
may be someone prompts better algorithm or you can find in the net a way how to calculate a mean value
of a large amount of data;
---

 

[FvM]

as a first approach - you can add e.g 16 values, divide the result by 16

Honestly speaking, I don't understand the purpose of the suggestions. If you want to implement a mean value calculation, you should use the correct formula. Or you get a different result. Precalculating blocks of 16 is possible, if the total number is a multiple of 16, but doesn't simplify much in this case. Increasing the accumulator width by 18 bits to account for MxN of 2^18 isn't a big deal for an FPGA.

If the MxN isn't a power of two, you can't avoid a divider. But a serial divider, that calculates the result in 32 clock cycles would be sufficient and has an acceptable resource footprint.

 

[j_andr]

Honestly speaking, I don't understand the purpose of the suggestions.

you are right,
I 'miscalculated' the size of the accumulator, somehow I thought it had to be many times bigger,
but the values are added, not multiplied;
---